JPH036123A - Logical input circuit - Google Patents

Abstract

PURPOSE:To prevent erroneous decision for a logic level due to the fluctuation of a power source noise from occurring by performing the serial connection of a P-channel MOSFET and an N-channel MOSFET by laminating them in two stages, respectively. CONSTITUTION:In an ordinary operation, the P-channel MOSFET Q1 is turned on, and the N-channel MOSFET Q4 is tuned off, and an input voltage level is outputted reversely. When an upward noise for the ground is inputted at a state where the input voltage level of an input terminal 1 is set at 'H', the P-channel MOSFET Q1 is turned off only for a period when the noise is inputted. Therefore, a level 'L' is continued to be outputted to an output terminal 2. Meanwhile, when a downward noise is inputted to a power source Vcc at the state where the input terminal 1 is set at 'L', the N-channel MOSFET Q4 is turned off. In such a manner, a level 'H' is continued to be outputted to the terminal 2. Therefore, no malfunction occurs even when the noise is inputted to the power source and the ground.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic input circuit that is used in semiconductor memory devices and receives TTL level input voltage.

[Conventional technology]

FIG. 2 is an input stage circuit diagram of an example of a conventional semiconductor memory device, in which 1 is an input terminal, 2 is an output terminal, and Q
! is P channel MOS FET, Qs is N
It is a channel MOSFET. To guarantee TTL level input voltage, the ability of N-channel MOSFET Q, is compared to that of P-channel MOSFET Q! is set larger than the capacity of

When input terminal 1 receives a high level input, N-channel MOSFET Qs becomes conductive (on), P-channel MOSFET Qz becomes non-conductive (off), and output terminal 2 becomes low level. Also, when a low level input is applied to the input terminal l, the P channel MOS P
E T Q t is on, N channel Mo5F E T
Qs is turned off and output terminal 2 becomes high level.

This circuit is a negative numerical inversion circuit, and normally,
It operates as shown in FIG. 3(a). That is, when the signal level A is higher than the determination level 1, it becomes high, and when it is lower than the determination level T, it becomes low.

[Problem to be solved by the invention]

The input stage circuit of the conventional semiconductor memory device described above is an inverting circuit, so as shown in FIG. 3(c), TT
When an input voltage high level of L level is given to input signal level C, if upward noise enters the ground side, the ground of the input stage circuit will rise from Ov, so the input WEE high level of TTL level will be lowered to low level. In addition, when the input voltage is low as shown in Figure 3 (b), if downward noise enters the power supply Vcc, the voltage Vcc of the input stage circuit will drop. Therefore, there is a drawback that the low input voltage is mistakenly judged as high level, and the opposite output level is output.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic input circuit that eliminates such drawbacks and eliminates erroneous determination of logic levels due to fluctuations in power supply noise.

[Means for Solving the Problems] The configuration of the logic input circuit of the present invention is such that between the power supply and the ground,
First and second P-channel MO3FETs and first and second N-channel MO3FETs are each connected in series in two stages, and a connection point between the second P-channel MO3FET and the first N-channel inter-O8FET is an output terminal, the gates of these MOSFETs are commonly connected to serve as an input terminal, the gate of the first P-channel MOSFET is connected to the ground, and the second N-channel MOSFET is connected to the ground.
It is characterized in that the gate of T is connected to the power supply.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In this embodiment, Q, , Q2 are P-channel MOSFEs.
T, Q3. Q4 is an N-channel O8FET.

Next, the operation of this embodiment will be explained.

(1) When no noise enters the power supply or ground: In this case, the input voltage to the P-channel MOSFET Q is at the ground level, so the MOSFET Q is in the on state. Further, the input voltage to the N-channel MOS FET Q4 is turned on at the power supply level, and operates in the same way as a normal inverting circuit.

(2) When upward noise enters the ground In this case, when the input voltage level of input terminal 1 is at a high level, if upward noise enters the ground, the P channel MOS F E
Since the input voltage of TQs changes from the ground (OV) level to the high level only during the period when noise is introduced,
During that period, P-channel MOSFET Q, is turned off. P channel MOS FETQ
! Even if it is turned on, it will no longer be possible to output a high level to output terminal 2. Therefore, a low level continues to be output to the output terminal 2.

(3) When downward noise enters the power supply Vcc In this case, when the input voltage level of input terminal l is low level, if downward noise enters the power supply Vcc, the N-channel MO8
F]li: Since the input voltage of T Q4 changes only during the period when it goes from the power supply level to the low level, the N-channel MOS FET Q4 is in the off state during that period. Therefore, N-channel MOS FETQ
Even if s is turned on, a low level cannot be output to the output terminal 2, and a high level continues to be output to the output terminal 2.

As explained above, this embodiment is less likely to malfunction even if noise enters the power supply or ground.

〔Effect of the invention〕

As explained above, the present invention has been achieved by adding a circuit that makes it difficult to malfunction even if noise enters the power supply and ground of a semiconductor memory device that has an input stage circuit that receives TTL level input voltage. It has the effect of making you stronger.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram of an example of a conventional logic input circuit, and Fig. 3 shows noise in the circuit of Fig. 2. FIG. 1...Input terminal, 2...Output terminal, Q
l, Q,...P channel MO3FET. Q31 Q4...N-channel MOSFET.

Claims (1)

[Claims] Between the power supply and ground, the first and second P-channel MO
The SFET and the first and second N-channel MOSFETs are each connected in series in two stages, and the connection point between the second P-channel MOSFET and the first N-channel MOSFET is used as an output terminal, and each of these MOSFETs is A logic input circuit characterized in that gates are commonly connected to serve as input terminals, the gate of the first P-channel MOSFET is connected to the ground, and the gate of the second N-channel MOSFET is connected to the power supply.