JPH0361355U

JPH0361355U -

Info

Publication number: JPH0361355U
Application number: JP12185589U
Authority: JP
Priority date: 1989-10-17
Filing date: 1989-10-17
Publication date: 1991-06-17

Description

[Brief explanation of drawings]

第１図Ａは本考案の一実施例の半導体集積回路
の上面図、第１図Ｂは第１図ＡのＡ−Ａ′線に沿
つて切断して見た断面図、第１図Ｃは第１図Ａの
Ｂ−Ｂ′線の断面図、第１図Ｄは第１図ＡのＣ−
Ｃ′線の断面図、第２図Ａは従来の半導体集積回
路の上面図、第２図Ｂは第２図ＡのＤ−Ｄ′線の
断面図、第２図Ｃは第２図ＡのＥ−Ｅ′線の断面
図、第２図Ｄは第２図Ａ図のＦ−Ｆ′線の断面図
である。１……半導体基板、２……電源配線、３……接
地配線、４……電源パツド、５……接地パツド、
６……誘電体層、７……カバー、８……拡散層。 FIG. 1A is a top view of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 1B is a cross-sectional view taken along line A-A' in FIG. 1A, and FIG. A sectional view taken along line B-B' in Figure 1A, and Figure 1D is a cross-sectional view taken along line C-- in Figure 1A.
2A is a top view of a conventional semiconductor integrated circuit, FIG. 2B is a sectional view taken along line D-D' of FIG. 2A, and FIG. 2C is a sectional view of FIG. 2A. 2D is a sectional view taken along line EE'. FIG. 2D is a sectional view taken along line FF' of FIG. 2A. 1... Semiconductor substrate, 2... Power wiring, 3... Ground wiring, 4... Power pad, 5... Ground pad,
6... Dielectric layer, 7... Cover, 8... Diffusion layer.

Claims

[Scope of utility model registration request]

The ground wiring and power wiring are connected via a dielectric layer,
A semiconductor integrated circuit characterized by overlapping each other to form a bypass capacitor.