JPH01143128U - - Google Patents

Info

Publication number
JPH01143128U
JPH01143128U JP3850188U JP3850188U JPH01143128U JP H01143128 U JPH01143128 U JP H01143128U JP 3850188 U JP3850188 U JP 3850188U JP 3850188 U JP3850188 U JP 3850188U JP H01143128 U JPH01143128 U JP H01143128U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
view
semiconductor integrated
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3850188U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3850188U priority Critical patent/JPH01143128U/ja
Publication of JPH01143128U publication Critical patent/JPH01143128U/ja
Pending legal-status Critical Current

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  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例による半導体集積
回路装置の上面図。第2図、第3図、第4図は電
極上に形成されたバンプの拡大上面図、拡大断面
図、斜視図。第5図はインナーリードと接合した
ときの斜視図、第6図は従来の半導体集積回路装
置の上面図、第7図、第8図、第9図は電極上に
形成されたバンプの拡大上面図、拡大断面図、斜
視図、第10図はインナーリードを接合したとき
の斜視図である。 図において、1は半導体基板、2はバンプ、3
はバンプ2上の凹部、4はインナーリードを示す
。なお、図中、同一符号は同一、または相当部分
を示す。
FIG. 1 is a top view of a semiconductor integrated circuit device according to an embodiment of this invention. FIG. 2, FIG. 3, and FIG. 4 are an enlarged top view, an enlarged sectional view, and a perspective view of bumps formed on the electrodes. FIG. 5 is a perspective view of a conventional semiconductor integrated circuit device when connected to an inner lead, FIG. 6 is a top view of a conventional semiconductor integrated circuit device, and FIGS. 7, 8, and 9 are enlarged top views of bumps formed on electrodes. , an enlarged sectional view, a perspective view, and FIG. 10 are perspective views when inner leads are joined. In the figure, 1 is a semiconductor substrate, 2 is a bump, and 3 is a semiconductor substrate.
indicates a recess on the bump 2, and 4 indicates an inner lead. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体基板の電極上に形成したバンプ部に、イ
ンナーリードとの接合部分に凹部を設けたことを
特徴とする半導体集積回路装置。
A semiconductor integrated circuit device characterized in that a bump portion formed on an electrode of a semiconductor substrate is provided with a recessed portion at a joint portion with an inner lead.
JP3850188U 1988-03-24 1988-03-24 Pending JPH01143128U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3850188U JPH01143128U (en) 1988-03-24 1988-03-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3850188U JPH01143128U (en) 1988-03-24 1988-03-24

Publications (1)

Publication Number Publication Date
JPH01143128U true JPH01143128U (en) 1989-10-02

Family

ID=31265045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3850188U Pending JPH01143128U (en) 1988-03-24 1988-03-24

Country Status (1)

Country Link
JP (1) JPH01143128U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123536U (en) * 1991-04-26 1992-11-09 サンケン電気株式会社 electronic components
JP2011216918A (en) * 2011-08-01 2011-10-27 Dainippon Printing Co Ltd Resin sealed type semiconductor device and circuit member for semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123536U (en) * 1991-04-26 1992-11-09 サンケン電気株式会社 electronic components
JP2011216918A (en) * 2011-08-01 2011-10-27 Dainippon Printing Co Ltd Resin sealed type semiconductor device and circuit member for semiconductor device

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