JPH0361373U - - Google Patents
Info
- Publication number
- JPH0361373U JPH0361373U JP12161889U JP12161889U JPH0361373U JP H0361373 U JPH0361373 U JP H0361373U JP 12161889 U JP12161889 U JP 12161889U JP 12161889 U JP12161889 U JP 12161889U JP H0361373 U JPH0361373 U JP H0361373U
- Authority
- JP
- Japan
- Prior art keywords
- solder
- land
- divided
- covered
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 239000004020 conductor Substances 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第１図ａ，ｂは本考案の第１の実施例にかかる
分割型ランドの正面図、側面図、第２図は本考案
の第１の実施例にかかる分割型ランドに半田が被
覆されたものの側面図、第３図は従来のランドに
半田が被覆されたものの側面図、第４図ａ，ｂは
本考案の第２の実施例にかかる分割型ランドの正
面図、側面図、第５図は本考案の第２の実施例に
かかる分割型ランドに半田が被覆されたものの側
面図である。
図面中、１……プリント基板、２……ランド、
２ａ，２ｂ，２ｃ……ランドの集合体、３……導
体パターン、４……レジスト、１２……ランドで
ある。
Figures 1a and b are front and side views of the split land according to the first embodiment of the present invention, and Figure 2 shows the split land covered with solder according to the first embodiment of the present invention. Figure 3 is a side view of a conventional land covered with solder, Figures 4a and b are front and side views of a split type land according to the second embodiment of the present invention, Figure 5 The figure is a side view of a split land coated with solder according to a second embodiment of the present invention. In the drawing, 1... printed circuit board, 2... land,
2a, 2b, 2c... aggregate of lands, 3... conductor pattern, 4... resist, 12... land.
Claims (1)
イツプ法により、表面が前記半田により被覆され
るランドにおいて、前記ランドが予めレジストに
より区分されて表面が複数に分割されることを特
徴とする分割型ランド。 (2) プリント基板ごと半田中に浸漬する半田デ
イツプ法により、表面が前記半田により被覆され
るランドにおいて、前記ランドが複数に分割され
た集合体として形成されることを特徴とする分割
型ランド。[Claims for Utility Model Registration] (1) In a land whose surface is covered with the solder by a solder dip method in which the entire printed circuit board is immersed in solder, the land is divided in advance by a resist and the surface is divided into a plurality of parts. A split-type land characterized by: (2) A divided land whose surface is covered with the solder by a solder dip method in which the entire printed circuit board is immersed in solder, and the land is formed as an aggregate divided into a plurality of parts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12161889U JPH0361373U (en) | 1989-10-19 | 1989-10-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12161889U JPH0361373U (en) | 1989-10-19 | 1989-10-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0361373U true JPH0361373U (en) | 1991-06-17 |
Family
ID=31669650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12161889U Pending JPH0361373U (en) | 1989-10-19 | 1989-10-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0361373U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006033170A1 (en) * | 2004-09-22 | 2006-03-30 | Murata Manufacturing Co., Ltd. | Wiring board and wiring board module |
-
1989
- 1989-10-19 JP JP12161889U patent/JPH0361373U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006033170A1 (en) * | 2004-09-22 | 2006-03-30 | Murata Manufacturing Co., Ltd. | Wiring board and wiring board module |
| KR100870645B1 (en) * | 2004-09-22 | 2008-11-26 | 가부시키가이샤 무라타 세이사쿠쇼 | Wiring board and wiring board module |
| US7679929B2 (en) | 2004-09-22 | 2010-03-16 | Murata Manufacturing Co., Ltd. | Wiring board and wiring board module |