JPH0361698U - - Google Patents
Info
- Publication number
- JPH0361698U JPH0361698U JP12138489U JP12138489U JPH0361698U JP H0361698 U JPH0361698 U JP H0361698U JP 12138489 U JP12138489 U JP 12138489U JP 12138489 U JP12138489 U JP 12138489U JP H0361698 U JPH0361698 U JP H0361698U
- Authority
- JP
- Japan
- Prior art keywords
- memory bank
- refresh
- memory
- control circuit
- timing signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004913 activation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Dram (AREA)
Description
第１図は本考案を実施したメモリ・バンクのリ
フレツシユ制御回路の構成を表わすブロツク図、
第２図は第１図に示した本考案回路の動作を表わ
すタイムチヤート、第３図は従来のメモリ・バン
クのリフレツシユ制御回路を表わす図である。
ｍｂ１，ｍｂ２……メモリ・バンク、Ｔ，Ｔ１
，Ｔ２……タイマ、Ｃ，Ｃ１，Ｃ２……リフレツ
シユ起動回路。
FIG. 1 is a block diagram showing the configuration of a memory bank refresh control circuit implementing the present invention.
FIG. 2 is a time chart showing the operation of the circuit of the present invention shown in FIG. 1, and FIG. 3 is a diagram showing a conventional memory bank refresh control circuit. mb1, mb2...Memory bank, T, T1
, T2...Timer, C, C1, C2...Refresh starting circuit.
Claims (1)
してリフレツシユ要求を発生するメモリ・バンク
のリフレツシユ制御回路において、各々の前記メ
モリ・バンクに、一定周期毎にリフレツシユ・タ
イミング信号を発し当該メモリ・バンク以外のメ
モリ・バンクを指定するメモリ・バンク選択信号
によりクリアされるタイマと、前記メモリ・バン
ク選択信号により現在アクセスされているメモリ
・バンクを検出して現在アクセスされていないメ
モリ・バンクに対してリフレツシユ要求を発生す
るリフレツシユ起動回路とを設けたことを特徴と
するメモリ・バンクのリフレツシユ制御回路。 (2) 前記リフレツシユ起動回路は現在アクセス
されているメモリ・バンクを検出して現在アクセ
スされていないメモリ・バンクに対してリフレツ
シユ要求を発生するとともにメモリ・バンクのリ
フレツシユ回数を計数して一定時間内の規定回数
を越えた際に前記リフレツシユ・タイミング信号
をマスクすることを特徴とする請求項(1)記載の
メモリ・バンクのリフレツシユ制御回路。[Claims for Utility Model Registration] (1) In a memory bank refresh control circuit that generates a refresh request to at least two or more memory banks, a refresh request is sent to each of the memory banks at regular intervals. A timer that is cleared by a memory bank selection signal that issues a timing signal and specifies a memory bank other than the memory bank in question, and a timer that detects the currently accessed memory bank by the memory bank selection signal and is currently accessed. 1. A refresh control circuit for a memory bank, comprising: a refresh start circuit that generates a refresh request for a memory bank that is not in use. (2) The refresh activation circuit detects the currently accessed memory bank, issues a refresh request to the currently unaccessed memory bank, and counts the number of times the memory bank is refreshed within a certain period of time. 2. The memory bank refresh control circuit according to claim 1, wherein the refresh timing signal is masked when the refresh timing signal exceeds a predetermined number of times.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12138489U JPH0361698U (en) | 1989-10-17 | 1989-10-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12138489U JPH0361698U (en) | 1989-10-17 | 1989-10-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0361698U true JPH0361698U (en) | 1991-06-17 |
Family
ID=31669418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12138489U Pending JPH0361698U (en) | 1989-10-17 | 1989-10-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0361698U (en) |
-
1989
- 1989-10-17 JP JP12138489U patent/JPH0361698U/ja active Pending
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