JPH0426499U - - Google Patents
Info
- Publication number
- JPH0426499U JPH0426499U JP6925290U JP6925290U JPH0426499U JP H0426499 U JPH0426499 U JP H0426499U JP 6925290 U JP6925290 U JP 6925290U JP 6925290 U JP6925290 U JP 6925290U JP H0426499 U JPH0426499 U JP H0426499U
- Authority
- JP
- Japan
- Prior art keywords
- refresh
- machine cycle
- time
- timer
- cycle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Dram (AREA)
Description
第１図は本考案の基本的構成を示す図、第２図
はＭＰＵと外部デバイス等が共通バスに接続され
ているシステム回路図、第３図はＭＰＵの動作を
示すタイミングチヤートである。
１……Ｄ−ＲＡＭ、２……ＭＰＵ、３……マシ
ンサイクル実行手段、４……リフレツシユ手段、
５……タイマー、６……タイマー制御手段、７…
…記憶手段、８……比較手段、９……調停手段。
FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a system circuit diagram in which the MPU and external devices are connected to a common bus, and FIG. 3 is a timing chart showing the operation of the MPU. 1...D-RAM, 2...MPU, 3...Machine cycle execution means, 4...Refresh means,
5...Timer, 6...Timer control means, 7...
...memory means, 8...comparison means, 9...mediation means.
Claims (1)
したマイクロプロセツサーユニツトにおいて、 マシンサイクルを実行するマシンサイクル実行
手段と、 内蔵Ｄ−ＲＡＭに対するリフレツシユを実行す
るリフレツシユ手段と、 タイマーと、 マシンサイクル実行手段のマシンサイクルの終
了またはリフレツシユ手段のリフレツシユの終了
の度にタイマーをリセツトするタイマー制御手段
と、 内蔵Ｄ−ＲＡＭのリフレツシユ周期より短い時
間を記憶した記憶手段と、 タイマーのカウント時間と記憶手段の時間を比
較する比較手段と、 比較手段がタイマーのカウント時間が記憶手段
の時間に達したことを検出した場合に、マシンサ
イクル実行手段をしてその時点でのマシンサイク
ルをダミーサイクル化し、リフレツシユ手段をし
てリフレツシユを実行させた後、マシンサイクル
実行手段をして前記にダミーサイクル化したサイ
クルを再実行させる調停手段 とを具備したことを特徴とするマイクロプロセツ
サーユニツトにおけるマシンサイクル／リフレツ
シユ制御装置。[Scope of Claim for Utility Model Registration] In a microprocessor unit having a refresh function for the built-in D-RAM, a machine cycle execution means for executing a machine cycle, a refresh means for executing a refresh for the built-in D-RAM, and a timer. and a timer control means that resets the timer each time the machine cycle execution means ends or refreshment of the refresh means ends, a storage means that stores a time shorter than the refresh cycle of the built-in D-RAM, and a timer count. a comparison means for comparing the time with the time in the storage means; and when the comparison means detects that the count time of the timer reaches the time in the storage means, the machine cycle execution means executes a dummy machine cycle at that point. In a microprocessor unit, the microprocessor unit is characterized in that it is equipped with an arbitration means for causing the machine cycle execution means to re-execute the cycle which has been made into a dummy cycle, after having caused the refresh means to execute the refresh. Machine cycle/refresh control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6925290U JPH0426499U (en) | 1990-06-28 | 1990-06-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6925290U JPH0426499U (en) | 1990-06-28 | 1990-06-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0426499U true JPH0426499U (en) | 1992-03-03 |
Family
ID=31604394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6925290U Pending JPH0426499U (en) | 1990-06-28 | 1990-06-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0426499U (en) |
-
1990
- 1990-06-28 JP JP6925290U patent/JPH0426499U/ja active Pending