JPH0486300U - - Google Patents
Info
- Publication number
- JPH0486300U JPH0486300U JP12508890U JP12508890U JPH0486300U JP H0486300 U JPH0486300 U JP H0486300U JP 12508890 U JP12508890 U JP 12508890U JP 12508890 U JP12508890 U JP 12508890U JP H0486300 U JPH0486300 U JP H0486300U
- Authority
- JP
- Japan
- Prior art keywords
- rams
- ram
- refresh
- memory
- refreshed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 7
- 239000013256 coordination polymer Substances 0.000 description 1
Landscapes
- Dram (AREA)
Description
第１図は本考案の機能ブロツク図、第２図は実
施例のブロツク構成図、第３図は第２図に示した
メモリコントロールの構成を示すブロツク図、第
４図ａは従来のメモリ空間を示す図、同図ｂは本
考案のメモリ空間を示す図、第５図ａは従来のＣ
ＰＵサイクルを示す図、第５図ｂは本考案のＣＰ
Ｕサイクルとリフレツシユタイミングを示す図、
第５図ｃはＣＰＵサイクルのそれぞれの処理期間
のタイミングを示すタイミングチヤートである。
１……複数のＲＡＭ、２……メモリセレクト手
段、３……リフレツシユ制御手段、２１……メモ
リセレクト回路、２２……ＲＡＭ ＲＦＳＨ回路
、２３……ＲＡＭ ＲＤ／ＷＲコントロール回路
。
Fig. 1 is a functional block diagram of the present invention, Fig. 2 is a block diagram of the embodiment, Fig. 3 is a block diagram showing the configuration of the memory control shown in Fig. 2, and Fig. 4a is a conventional memory space. Figure 5b is a diagram showing the memory space of the present invention, Figure 5a is a diagram showing the conventional C
A diagram showing the PU cycle, Figure 5b is the CP of the present invention.
Diagram showing U cycle and refresh timing,
FIG. 5c is a timing chart showing the timing of each processing period of a CPU cycle. DESCRIPTION OF SYMBOLS 1...Plural RAMs, 2...Memory selection means, 3...Refresh control means, 21...Memory select circuit, 22...RAM RFSH circuit, 23...RAM RD/WR control circuit.
Claims (1)
ＲＡＭと、 前記複数のＲＡＭの内の少なくとも１つをデー
タの読み出しまたは書き込みするＲＡＭとして選
択するメモリセレクト手段と、 前記メモリセレクト手段によつて前記複数のＲ
ＡＭのいずれも選択されていない時には、前記複
数のＲＡＭの内の何れか１つにリフレツシユ動作
させ、且つ前記メモリセレクト手段によつて何れ
か１つのＲＡＭが選択されている時には、その選
択されたＲＡＭ以外の前記複数のＲＡＭの内の１
つにリフレツシユ動作を行わせるリフレツシユ制
御手段とを具備することを特徴とするＲＡＭリフ
レツシユ回路。[Claims for Utility Model Registration] A plurality of RAMs that require a data refresh operation; a memory selection means for selecting at least one of the plurality of RAMs as a RAM from which data is read or written; and the memory selector. The plurality of R
When none of the RAMs is selected, one of the plurality of RAMs is refreshed, and when one of the RAMs is selected by the memory selection means, the selected RAM is refreshed. One of the plurality of RAMs other than RAM
A RAM refresh circuit comprising: a refresh control means for causing a refresh operation to be performed in a RAM refresh circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12508890U JPH0486300U (en) | 1990-11-29 | 1990-11-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12508890U JPH0486300U (en) | 1990-11-29 | 1990-11-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0486300U true JPH0486300U (en) | 1992-07-27 |
Family
ID=31872708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12508890U Pending JPH0486300U (en) | 1990-11-29 | 1990-11-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0486300U (en) |
-
1990
- 1990-11-29 JP JP12508890U patent/JPH0486300U/ja active Pending
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