JPH0361872A - Clock control circuit for delay test - Google Patents

Abstract

PURPOSE:To prevent breakdown of activating conditions and to perform a test at high reliability and high diagnostic rate in a short time by conducting the test under the state wherein the application of clocks to latches other than a source latch and a target latch is suppressed. CONSTITUTION:Latches 1 constituting an LSI are divided into a plurality of classes. OS latches 2 for controlling the application-suppression of clocks are provided for the latches. The latches 2 corresponding to a source latch 1-1 and a target latch 1-2 which perform a delay test are made to scan-in and are set so as to obtain effective values. A clock is applied to the latch 1-1, and its output is propagated. After a specified time has elapsed, a clock is applied to the latch 1-2, and its state is received. Thus, the delay test is performed. Therefore the delay test is performed under the state wherein the latches 2 are scanned-in and the application of the clocks to the latches 1 other than the latches 1-1 and 1-2 is suppressed.

Description

[Detailed Description of the Invention] [Summary] Regarding a clock control circuit that controls a clock that performs a delay test, an OS launch that controls application/inhibition of a clock is provided at a launch that performs FII on an LSI, and scans into these OS launches. The purpose of this is to suppress the application of clocks to launches other than the source latch and target latch, thereby preventing destruction of the activation conditions during delay tests and enabling delay tests with high accuracy and high diagnostic efficiency. The launches that hold the data constituting the latches are classified into multiple groups, and an OS latch is provided for each of these classified latches to control clock application/inhibition. Scan in and set the OS launch to a valid value, apply a clock to the source latch to propagate its output, and after a predetermined period of time, apply a clock to the target latch to capture its state and set the delay. Configure to test.

[Industrial application field]

The present invention relates to a clock control circuit that controls a clock for performing a delay test.

[Problems to be solved by conventional technology and invention] Conventionally, L
The SI delay test was conducted as follows.

(1) From the latch that is the starting point for an external input or state change (hereinafter referred to as the source latch) to the latch that is the destination (
(hereinafter referred to as target latch) or set the internal state value so that the state change propagates through the path to the external output (
activation of state propagation pathways).

(2) Apply a clock with the current state of the source latch and the opposite human power set to the source latch, and after the time required for the state change to propagate to the target latch,
Apply clock to target latch. If there is a defective element on the propagation path, the old input state is taken into the target latch, so the presence of the defective element becomes clear.

The LST delay test is performed using the above procedure. In response to applying a clock to the source latch, the activation conditions of the propagation path are destroyed, for example, as shown in Figure 1. There is a problem. In order to prevent the activation conditions of this propagation path from being destroyed, it is desirable to apply a clock only to the source latch. However, in conventional general logic circuit structures, this There is a problem in that it is difficult to implement this method for routes.

The present invention provides clock supply/
An OS launch is provided to control the inhibition, and by scanning into these OS launches, the application of the clock to latches other than the source latch and target latch is inhibited, preventing destruction of activation conditions during delay testing, and achieving high accuracy and The aim is to enable delay testing with a high diagnostic rate.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In FIG. 1, lunch 1 is a launch that holds data constituting the LSI.

The OSS latch is a launch that scans in and sets data for controlling clock application/inhibition to the latch 1.

[Effect]

As shown in FIG. 1, the present invention classifies latches l constituting an LSI into a plurality of groups, provides OS latches 2 for controlling clock application/inhibition for each of these classified latch l, and performs a delay test. source latch 1
-1 and the OS latch 2 corresponding to the target latch 1-2 are scanned in and set to a valid value, a clock is applied to the source latch 1-1 to propagate its output, and after a predetermined period of time the clock is clocked in. The target latch 1
-2, the state is captured, and a delay test is performed.

Therefore, by performing a delay test while scanning into OS latch 2 and suppressing the application of clocks to latches l other than source latch l-1 and target latch l-2, the activation conditions during the delay test can be destroyed. This makes it possible to perform delay tests with high accuracy and high diagnostic rate.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 to 3.

In FIG. 1, latch 1 is a launch that holds data for itc of the LSI, and applies a clock to latch 1 according to the data set in O3 (only scan) latch 2. Alternatively, it is configured to be able to suppress the application. here,
The 16 latches 1 are classified into four groups, and clocks can be applied/inhibited based on data scanned into and set in OS (1) to OS (4).

OS latch 2 is here O3+1) or OS+3
1, it scans in and supplies set data to the corresponding latch 1, applies a clock to the latch 1, or suppresses the application of the clock. Here, 03fll and O3+31 are set to "0" (valid value) to enable applying the clock CLKI to the source latch 1-1 in the first row and the clock CLK2 to the target latch l-2 in the third row. -・OS +21
,OS! 4) is set to "l" (invalid value) to suppress the application of the clock to the latches l in the second and fourth rows. Therefore, for example, at the position shown in ■, the clock CLK
The activation of the state propagation path is not destroyed by the application of I,2.

Next, the operation of the configuration shown in FIG. 1 will be explained in detail in accordance with the order shown in the flowchart of FIG.

In FIG. 2, ■ determines the bus to be tested.

This determines the bus on which the delay test shown using the thick line in FIG. 1 is to be performed. By determining this bus, the source latch 1-1 and target latch 1-2 are determined.

O is source latch 1-1 and target latch 1-2
OSS latches corresponding to 2 are scanned in and set to valid values, and the other OS launches 2 are scanned in and set to invalid values. This corresponds to the first source latch 1-1 in FIG.
O3 (1) corresponding to row and target latch 1-
The OS +31 corresponding to the third row of 2 is scanned in and set to the valid value "O", and the other OS +21, (4) is scanned in and set to the invalid value "1".

Otherwise, when changing the rising edge: scan in "0" to source latch 1-1 and
After setting the input terminal to 1'', apply the clock CLK 1 to the source latch 1-1, send “1” to the output, and start propagating the data toward the target latch 1-2. In order to change the fall, it is sufficient to scan in "1" to the source latch 1-1 and scan in "O" to the input terminal of the source latch 1-1.

(2) After a predetermined period of time has elapsed, the clock CLK2 is applied to the target latch l-2 to capture data.

■ determines whether the value of target latch 1-2 is 1■". If YES, data is propagated from source latch 1-1 to target latch 1-2 and is taken in, so the delay On the other hand, in the case of No, the delay is determined to be abnormal (NG).

As described above, the valid value is scanned into the corresponding OS latch 2 and the source latch 1-4 and target latch 1-4 are scanned in.
By testing the data delay from the source latch 1-1 to the target latch 1-2 while suppressing the application of the clock to the other 7 chips, it is possible to prevent the activation conditions during the delay test from being destroyed. It becomes possible to perform delay tests with high accuracy and high diagnostic rate.

FIG. 3 shows a configuration diagram of one embodiment of the present invention.

In FIG. 3, O3L (only scan latches) 1 to 03L4 are OS latches 2.

The source latch t-t and the target latch L-2 are O3
Since the valid value a01 is scanned in and set to L 1.08L3, the clock CLK 1 and the clock CLK
2 is set to be applied to each. 03L
Since the invalid value "l" is scanned in and set in 2.08L4, the application of the clock to the latch l corresponding to these is inhibited. The operation of this is the same as in FIG.
Scan in and set the invalid value "1" to L2.03L4. (2) Scan in and set ``0'' (or 1'') to source latch 1-1, and set “1” (or “0”) to the input terminal. (3) Set clock CLK1 to source latch 1-1, and after a predetermined period of time, clock CLK2 is applied to target latch 1-2.
to be applied. At this time, when the data taken into the target latch 1-2 is 1) (or 10''), it is determined that the delay is normal, and on the other hand, when it does not change, it is determined that the delay is abnormal.

〔Effect of the invention〕

As described above, according to the present invention, the delay test is performed in a state where the OS latch 2 is scanned in and the application of clocks to the launches 1 other than the source latch 1-1 and the target latch 1-2 is suppressed. This prevents the activation conditions from being destroyed during the delay test, allowing the delay test to be performed in a short time with high accuracy and high diagnostic efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a flowchart explaining the operation of the present invention, FIG. 3 is a structural diagram of one embodiment of the present invention, and FIG. 4 is an explanatory diagram of the prior art. In the figure, l represents a latch, 1-1 represents a source latch, 1-2 represents a target latch, and 2 represents an OS latch. X Invention Movement A Public Holiday Month 70 - Chart Bird Chart

Claims (1)

[Claims] In a clock control circuit that controls a clock for performing a delay test, latches (1) that hold data constituting an LSI are classified into a plurality of groups, and clocks are applied to these classified latches (1). /
OS latches (2) are provided to control inhibition, and the OS latches (2) corresponding to the source latch (1-1) and target latch (1-2) on which the delay test is to be performed are set to valid values. Scan in and set, apply the clock to the source latch (1-1) and propagate its output, and after a predetermined time, apply the clock to the target latch (1-2) to capture its state and perform a delay test. A clock control circuit for delay testing, characterized in that it is configured to perform the following.