JPH0736770A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor memory device in which the timing design of a controller, which is an external control logic circuit, is very easy. A memory 12 that operates in synchronization with an external clock signal CLK, an address signal ADD that is output to the memory 12, and a data read instruction signal CTRL that instructs reading of data DATA are output to the memory 12. CP that exchanges data DATA with
U11 and a controller 14 that outputs a chip enable signal CE _N to the memory 12 in response to a data read instruction signal CTRL, and an output enable signal when the chip enable signal CE _N is output. The circuit for generating the
2 itself enables timing control of the output start time and output end time of the read data DATA.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a synchronous dynamic RAM or static RAM.
The present invention relates to a semiconductor memory device suitable for use in, for example,

[0002]

2. Description of the Related Art A conventional example of this type of semiconductor memory device is shown in FIG. In the figure, the CPU 41 outputs an address signal ADD to the memory 42 via the address bus 43 in synchronization with a clock signal CLK from the outside, and a data read instruction for instructing the reading of data from the memory 42. The signal CTRL is output. Note that, in this example, for simplification of description, a system in which one memory 42 is connected to the CPU 41 is illustrated, but in reality, one CPU 41 has a plurality of memories and I / Os.
Will be connected.

The data read instruction signal CTRL output from the CPU 41 is supplied to the controller 44. The controller 44 sends the chip enable signal CE _N to the memory 42 in response to the data read instruction signal CTRL.
(The subscript _N represents negative logic, and the same applies hereinafter), and the clock signal CL from the outside is output.
The output enable signal OE _N is output based on K. The memory 42 is a chip from the controller 44.
When the enable signal CE _N is selected and the output enable signal OE _N is output from the controller 44, the data DATA is output to the CPU 41 via the data bus 45.

Next, regarding the operation of the conventional apparatus having the above-mentioned structure,
A description will be given based on the timing chart of FIG. CPU
41 indicates the address signal A to the memory 42 at time t _1.
Outputs DD and outputs data read instruction signal CTR
Output L. The controller 44 receiving the data read instruction signal CTRL
The enable signal CE _{N is set} to low level, and the memory 42 sets the data DATA based on the clock signal CLK.
Start counting the time until it can output.

The controller 44 waits until the memory 42 can output the data, and sets the output enable signal OE _N for the memory 42 to the low level at time t ₂ . The memory 42 outputs the output enable signal OE.
Upon receiving the _N, data from time t ₂ to time t _OE after
The data DATA is output to the bus 45. The controller 44, after outputting an output enable signal OE _N only the necessary time for the memory 42, the time t ₃
Then, the output enable signal OE _N is returned to the high level again. As a result, the memory 42 _{puts the} output in the high impedance state after the time t _{OHZ has} elapsed from the time t ₃ .

[0006]

However, in the conventional semiconductor memory device having the above structure, the controller 44 generates the output enable signal OE _N for permitting the output of the data DATA to the memory 42. Therefore, the system designer has a CPU 41 and a memory 42.
Since it is necessary to design the timing of the controller 44 based on the timing relationship based on the combination with the above, it is very difficult to design the timing of the controller 44. The present invention has been made in view of the above problems,
It is an object of the present invention to provide a semiconductor memory device in which the timing design of a controller, which is an external control logic circuit, is very easy.

[0007]

To achieve the above object, in a semiconductor memory device according to the present invention, a memory that operates in synchronization with an external clock signal, and an address signal is output to this memory. The CPU includes a CPU that outputs a data read instruction signal for instructing data reading and exchanges data with the memory, and a controller that outputs a chip enable signal to the memory in response to the data read instruction signal. However, the memory has a built-in signal generation circuit that generates an output enable signal based on a clock signal from the outside when the chip enable signal is output, and sends it to the CPU in response to the output enable signal. It is configured to output data.

[0008]

In the semiconductor memory device having the above structure, by providing a circuit for generating the output enable signal based on the clock signal from the outside in the memory, the output start time and the output end time of the read data can be controlled by the memory itself. Timing control becomes possible. Therefore, the controller that controls the memory does not need to generate the output enable signal, so that the timing design of the controller can be very easily realized when designing the controller.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a system block diagram showing an embodiment of a semiconductor memory device according to the present invention. In FIG. 1, the CPU 11 operates in synchronization with a clock signal CLK from the outside, and operates with respect to the memory 12 via an address bus 13
The address signal ADD is output via the same and the data read instruction signal CTRL for instructing the reading of the data DATA from the memory 12 is output. In the present embodiment, for simplification of the description, a system in which one memory 12 is connected to the CPU 11 is shown, but in reality, a plurality of memories and I / Os are provided for one CPU 11.
Shall be connected.

The data read instruction signal CTRL output from the CPU 11 is supplied to the controller 14. This controller 14 operates in synchronization with an external clock signal CLK, outputs a write enable signal WE _N to the memory 12, and responds to a data read instruction signal CTRL to the chip 12 for the memory 12. The enable signal CE _N is output. The memory 12 operates in synchronization with an external clock signal CLK, generates an output enable signal when the chip enable signal CE _N is supplied from the controller 14, and responds to the output enable signal in response to the output enable signal. The data DATA is output to the data bus 15.

FIG. 2 is a block diagram showing a circuit configuration of a part of the internal circuit of the memory 12. The internal circuit includes an output enable signal generation circuit 21 that generates an output enable signal oe _N in synchronization with the clock signal CLK when the chip enable signal CE _N output from the controller 14 is applied. , Data data supplied from a memory array (not shown),
A data output circuit 22 for outputting in response to the output enable signal oe _N is provided. At the input stage of the output enable signal generation circuit 21, a write
When the chip enable signal CE _N transits from a high level to a low level while the enable signal WE _N is at a high level, or when both the write enable signal WE _N and the chip enable signal CE _N are at a low level An ATD (Address Transition Detector) circuit 23 that generates an ATD _N pulse when the address signal ADD makes a transition is provided.

The ATD _N pulse output from the ATD circuit 23 becomes the S input of the RS flip-flop 24 in the next stage. The Q output q ₁ of this RS flip-flop 24 is D
It becomes the D input of the flip-flop 25. The D flip-flop 25 has a clock signal CLK from the outside as a clock input. The Q output q ₂ of the D flip-flop 25 becomes the R input of the RS flip-flop 24 of the previous stage, and its Q _N output is the D input of the D flip-flop 26 of the next stage.
It becomes an input. The D flip-flops 25 and 26 form a 2-clock counter. The D flip-flop 26 receives an external clock signal CLK as a clock input, and outputs its Q _N output as an output enable signal o.
e _N.

On the other hand, the data output circuit 22 has a data latch circuit 27 which receives data data supplied from a memory array (not shown) as a D input and an output enable signal oe _N as a G input, and an output enable signal oe. It is composed of an output buffer 28 that amplifies data data in synchronization with _N and outputs it as data DATA to the outside. The output buffer 28 has a NAND gate 29 that receives the Q output of the data latch circuit 27 as one input.
Similarly, a negative logic NOR gate 30 having the Q output of the data latch circuit 27 as one input and the output enable signal oe _N as the other input, and the NAND gate 29 which inverts the output enable signal oe _N And an PMOS transistor 32 and an NMOS transistor 33, which are connected in series between the power supply V _DD and the ground and have respective outputs of the NAND gate 29 and the NOR gate 30 as gate inputs.

Next, the circuit operation of the internal circuit of the memory 12 having the above structure will be described with reference to the timing chart of FIG. At time t _{1 when} the clock signal CLK rises, the address signal ADD and the chip enable signal CE _N
When the transition occurs, the ATD _N pulse is generated from the ATD circuit 23 and the RS flip-flop 24 is set. This causes the Q output q ₁ of the RS flip-flop 24 to transition from low level to high level. At time t ₂ at the next rising edge of the clock signal CLK, the D flip-flop 25 becomes RS
The Q output q ₁ of the flip-flop 24 is latched, and the RS flip-flop 24 is reset by the Q _N output.

At the falling time t ₃ of the same clock signal CLK, the D flip-flop 26 latches the Q output q ₂ of the D flip-flop 25 and lowers the output enable signal oe _N which has been high level until then. Level. When the output enable signal oe _N becomes low level, the data latch circuit 27 latches the data data from the memory cell, and the output buffer 28 becomes active to amplify the data latched in the data latch circuit 27. And output as data DATA to the outside. D at the time t ₄ at the rising edge of the next clock signal CLK
The flip-flop 25 latches the low-level Q output q ₁ of the RS flip-flop 24 and sets the Q-output q ₂ that was high level until then to the low level.

When the clock signal CLK falls at time t ₅ , the D flip-flop 26 becomes the D flip-flop 2.
The low level Q output q _{2 of 5} is latched, and the low level output enable signal oe _N is made high. When the output enable signal oe _N becomes high level, the data latch circuit 27 causes the input data data to be output.
At the same time, while in transparent mode,
Since the output of the output buffer 28 is in a high impedance state, the output data DATA has a high impedance.
When the address signal ADD transits again at time t ₄ , the same operation as that started at time t ₁ is performed.

In the above embodiment, the start of the memory read cycle is detected by using the ATD circuit 23, but the method of detecting the start of the memory read cycle is not limited to this. No, for example CP
The bus control signal (S ₀ / S ₁ ) or the like from U11 may be used. Further, in the above embodiment,
Data DATA is output at time t ₃ 1.5 clocks after the start time t ₁ of the memory read cycle,
Although the circuit configuration for returning the data DATA to the high impedance state at time t ₅ after the clock is shown, it is possible to create an arbitrary output state by changing the generation method of the D input of the D flip-flop 26.

[0018]

As described above, according to the present invention,
The memory is controlled by incorporating a circuit that generates an output enable signal based on an external clock signal into the memory and enabling the timing control of the output start time and output end time of the read data by the memory itself. Since the controller does not need to generate the output enable signal, the timing design of the controller can be realized very easily in designing the controller. Furthermore, there is an effect that the configuration of the controller itself, which is an external control logic circuit, can be simplified. Therefore, the semiconductor memory device according to the present invention is
It is suitable for use in a synchronous dynamic RAM or static RAM.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a block diagram showing the configuration of part of the internal circuit of the memory.

FIG. 3 is a timing chart provided for explaining a circuit operation according to the present invention.

FIG. 4 is a block diagram showing a conventional example of a semiconductor memory device.

FIG. 5 is a timing chart for explaining the circuit operation of the conventional example.

[Explanation of symbols]

 11, 41 CPU 12, 42 Memory 13, 43 Address Bus 14, 44 Controller 15, 45 Data Bus 21 Output Enable Signal Generation Circuit 22 Data Output Circuit 23 ATD Circuit 24 RS Flip Flop 25, 26 D Flip Flop 27 Data latch circuit 28 Output buffer

Claims (1)

[Claims] 1. A memory which operates in synchronization with a clock signal from the outside, and outputs a data read instruction signal for outputting an address signal to the memory and instructing data reading, to and from the memory. CPU that exchanges data
And a controller that outputs a chip enable signal to the memory in response to the data read instruction signal, wherein the memory outputs the chip enable signal based on the clock signal when the chip enable signal is output. A semiconductor memory device comprising a signal generation circuit for generating a switch enable signal and outputting data to the CPU according to the output enable signal.