JPH0362302B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device capable of high-speed operation.

[Conventional technology]

A conventional active semiconductor device that is expected to operate at high speeds utilizes high-mobility two-dimensional electrons at the hetero-interface of a semiconductor selectively doped with impurities.
FET (Field Effect Transistor) (hereinafter referred to as
2DEGFET〔Two dimensional Electron Gas
(For example, Japan Journal of Applite Physics [Jpn.J.Appl.Phys.19 (1980) L255]). this
2DEGFET is MOSEFT (Metal Oxide
Like Semiconductor FETs, it has a simple operating principle, structure, and process, making it suitable for high integration.

Figure 3 shows the structure of 2DEGFET. In FIG. 3, 1 is an insulating semiconductor substrate, 2 is a first semiconductor layer made of a first semiconductor provided on the substrate 1, and 3 is a first semiconductor layer provided on the surface of the first semiconductor layer 2.
A second semiconductor having one conductivity type that has a smaller electron affinity and a larger sum of electron affinity and forbidden band width than the semiconductor of
4 is a two-dimensional carrier layer formed at the interface between the first semiconductor layer 2 and the carrier supply layer 3; 5 is a two-dimensional carrier layer formed on the surface of the carrier supply layer 3 and has a shot key junction with the carrier supply layer; 6 is a source electrode that makes electrical contact with the two-dimensional carrier layer 4 via the carrier supply layer 3, and 7 is a drain electrode similar to the source electrode 5. The operation of this 2DEGFET will be explained using an n-type semiconductor for the carrier supply layer 3 and a diagram showing the band structure between the source and drain.

FIG. 4 shows a schematic band structure extending from below the source electrode to below the drain electrode on the surface of the first semiconductor layer shown in FIG. Elements with the same numbers as in Fig. 3 are equivalent to the elements in Fig. 3 and have the same function. 8 is under the gate electrode, 9 is under the source electrode, 10 is under the drain electrode, Ec is the conduction band edge, Ev
indicates the charged zone edge and Ef indicates the Fermi order. FIG. 4A is a band diagram in a thermal equilibrium state, and FIG. 4B is a band diagram when a positive voltage is applied to the gate and a two-dimensional carrier layer 4 is formed between the source and drain.

When the gate voltage is 0V (thermal equilibrium state),
The lower gate electrode 8 is depleted due to the extended depletion layer due to the shot junction between the gate electrode 5 and the carrier supply layer 3, so even if a voltage (drain voltage) is applied between the source and drain, electrons will not flow from the source electrode 6. It cannot move to the drain electrode 7. On the other hand, when a positive voltage is applied to the gate electrode 5, electrons are induced on the substrate surface, and a two-dimensional carrier layer 4 is formed, resulting in the band structure shown in FIG. 4B. In this state, there is no longer a barrier formed by the depletion layer on the substrate surface between the source and drain, and electrons can easily move from the source electrode 6 to the drain electrode 7. In this way, 2DEGFET is MOSFET
Similarly, the current between the source and drain (drain current) is controlled by the gate voltage.

[Problem that the invention seeks to solve]

In 2DEGFET, in principle, the mutual conductance (the change in drain current with respect to the change in gate voltage) is simply proportional to the gate voltage, so the load driving ability is small. Since the rate of delay due to driving increases, high-speed operation is suppressed. To solve this problem, it is necessary to strengthen the nonlinearity of mutual conductance and increase the load driving ability, similar to bipolar transistors.

An object of the present invention is to eliminate the drawbacks of conventional 2DEGFETs and provide a semiconductor device capable of ultra-high-speed operation.

[Means for solving problems]

The semiconductor device of the present invention has a first semiconductor device with an extremely low impurity concentration.
a first semiconductor layer formed of a semiconductor; and a second semiconductor layer provided on the surface of the first semiconductor layer and having one conductivity type having a smaller electron affinity and a larger sum of electron affinity and forbidden band width than the first semiconductor. a carrier supply layer made of a semiconductor; a gate electrode provided on the carrier supply layer and forming a shot key junction with the carrier supply layer; and a carrier supply layer sandwiching the gate electrode near the surface of the first semiconductor layer. It is characterized by having a source region and a drain region made of degenerate first semiconductor layers having different conductivity types, and a source region and a drain region forming ohmic contact with the source region and the drain region, respectively.

[Effect]

In the structure of the present invention, the drain current is controlled by changing the tunneling probability of carriers between the source and the channel region surface and between the channel region surface and the drain using the gate voltage. Since the tunneling probability changes as an exponential function of the potential difference and the pn junction depletion layer thickness, the mutual conductance has large nonlinearity.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic sectional view showing an embodiment of the present invention. In FIG. 1, those with the same numbers as in FIG. 3 are equivalent to those in FIG. 3 and have the same functions, and 11 and 12 supply carriers with the gate electrode 5 in between near the surface of the first semiconductor layer 2. layer 3
The source region and the drain region are made of a degenerate first semiconductor having a conductivity type different from that of the first semiconductor. These source region 11 and drain region 12,
The source electrode 6 and the drain electrode 7 each form an ohmic contact.

As an example of each layer in this embodiment, the semiconductor substrate 1
Cr-doped semi-insulating GaAs as the first semiconductor layer 2, undoped GaAs as the first semiconductor layer 2, and a carrier supply layer 3 with a thickness of about 200 Å and an acceptor concentration of 3×
P ⁺ -Al _0.5 Ga _0.5 As of about 10 ¹⁸ cm ^-3 , source region 1
1 and the drain region 12 with a donor concentration of 1
×10 ¹⁹ cm ^-3 n ⁺ -GaSa, W as gate electrode 5, source electrode 6 and drain electrode 7
There is AuGe/Au. Further, the distance between the source and drain is about 1000 Å.

The operation of this embodiment will be explained using the above-mentioned materials and with reference to FIG. 2, which shows this band structure.

FIG. 2 schematically shows a band structure extending from the source region 11 in FIG. 1 to the drain region 12 via the surface of the first semiconductor layer below the gate electrode 8. FIG. Items with the same numbers as those in Figures 1, 3, and 4 are numbered 1,
It is equivalent to Figures 3 and 4 and performs the same function.
Figure 2A is a band diagram in a thermal equilibrium state, and Figure 2B is a band diagram when a negative voltage is applied to the gate electrode.
Two-dimensional carrier layer (two-dimensional hole gas) degenerated into
FIG. 4 is a band diagram when 4 is formed.

In the thermal equilibrium state shown in FIG. 2A, the source region 1
An electron barrier is formed by a pn junction between the n ⁺ -GaAs of the source region 1 and the source region 12 and the non-degenerate two-dimensional carrier layer 4 below the gate electrode 8. Since the hole concentration in the two-dimensional carrier layer 4 is not high enough to cause degeneracy, the width of this barrier is as wide as 100 Å or more, and there is almost no probability that holes will pass through this barrier by the tunnel effect. Therefore, even if a minute voltage of about 0.1V is applied between the source and drain, almost no drain current flows. On the other hand, as shown in FIG. 2B, if a negative voltage is applied to the gate electrode to induce enough holes to cause degeneration in the two-dimensional carrier layer 4,
This two-dimensional carrier layer 4 becomes a degenerate semiconductor. As a result, the width of the pn junction barrier between the source region 11 and the drain region 12 becomes extremely narrow (100 Å or less), and the probability of passing through this barrier by the tunnel effect increases. Then, a drain current starts to flow by applying a drain voltage. Since tunnel current changes exponentially with junction potential difference and depletion layer width, drain current and transconductance exhibit strong nonlinearity with respect to gate voltage. Furthermore, because the tunnel effect is the basic operating principle of this device, the electron transit time is extremely short, less than 1 ps.

Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described. First, a first semiconductor layer 2 is formed on the surface of a Cr-GaAs substrate 1 by molecular beam epitaxy.
Undoped GaAs of about 5000 Å and P ⁺ -Al _0.5 Ga _0.5 As of about 200 Å are deposited as the carrier supply layer 3. W is vapor-deposited thereon and shaped into the shape of a gate electrode. Next, using this gate electrode 5 as a mask, Si ions are implanted into the substrate and annealed to form a source region 11 and a drain region 12. After that, contact holes are made in the carrier supply layer above the source and drain regions, and the AuG/
The electrodes are completed by vapor depositing Au and shaping them into the shapes of the source and drain electrodes. As described above, the manufacturing method is very easy and suitable for high integration.

As described above, the semiconductor device of this example is easy to manufacture, eliminates the drawbacks of 2DEGFET, and has large nonlinearity in mutual conductance like a bipolar transistor, so it can achieve high integration and high-speed operation. enable.

In the embodiment of the present invention described above, only the p-type two-dimensional carrier layer was shown, but
It is clear that the present invention is equally applicable to an n-type two-dimensional carrier layer in which the conductivity type of the semiconductor in each region is reversed. Furthermore, in order to increase the withstand voltage and reduce parasitic capacitance, it is preferable to use an insulator for the substrate and to reduce the thickness of the first semiconductor layer.

In addition, although only GaAs/Al _0.5 Ga _0.5 As was shown as a semiconductor, other semiconductors such as Si/SiC, etc.
InGaAs/InAlAs, InAs/InGaAs, InGaAs/
Compound semiconductors such as InP, GaSb/AlSb, etc.
Compound semiconductors such as HgTe/CbTe, CdSe/ZnCdSeTe, and other various semiconductors may also be used.
However, since the densities of states in the conduction band and charge band are different in each semiconductor, the concentration of impurities that cause degeneracy is different, and the source and drain regions of the present invention do not contain impurities at a high concentration that causes sufficient degeneration. It is necessary to contain it.

〔Effect of the invention〕

As described above, the semiconductor device of the present invention has a structure suitable for integration and has a large load driving ability, so it is promising as a highly integrated and ultra-high speed device.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of one embodiment of the present invention, FIGS. 2A and B are band diagrams in its thermal equilibrium state and a band diagram when a negative voltage is applied to the gate electrode, and FIG. 3 is a conventional FIGS. 4A and 4B are schematic cross-sectional views of the 2DEGFET shown in FIG. DESCRIPTION OF SYMBOLS 1... Substrate, 2... First semiconductor layer, 3... Carrier supply layer, 4... Two-dimensional carrier layer, 5...
Gate electrode, 6...Source electrode, 7...Drain electrode, 8...Below gate electrode, 9...Below source electrode, 10...Below drain electrode, 11...Source region, 12...Drain region, Ec... ...conduction band edge,
Ev...Charge band edge, Ef...Fermi rank.

Claims (1)

[Claims] 1 A first semiconductor made of a first semiconductor with an extremely low impurity concentration
a carrier supply comprising a semiconductor layer and a second semiconductor provided on the surface of the first semiconductor layer and having one conductivity type that has a smaller electron affinity than the first semiconductor and a larger sum of electron affinity and forbidden band width. a gate electrode provided on the carrier supply layer and forming a Schottky junction with the carrier supply layer, and a degenerate layer having a conductivity type different from that of the carrier supply layer, sandwiching the gate electrode near the surface of the first semiconductor layer. 1. A semiconductor device comprising: a source region and a drain region made of a first semiconductor; and a source region and a drain electrode forming ohmic contact with the source region and the drain region, respectively.