JPH0546705B2 - - Google Patents

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor device.

(Conventional technology) A typical conventional semiconductor device is a Si MOSFET.
(Metal Oxide Semiconductor Field Effect
Transistor) and bipolar transistor. Among them, MOSFETs are suitable for high integration and are widely used because of their simple operating principle, structure, and manufacturing process.

Figure 3 shows a cross-sectional view of the MOSFET.

In FIG. 3, 1 is a p-type semiconductor substrate, 2 is an n-type semiconductor substrate, and 2 is an n-type semiconductor substrate.
Source region with type impurity, 3 is source region 2
and the source electrode forming an ohmic junction, 4 is n
a drain region having a type impurity; 5 a drain electrode forming an ohmic contact with the drain region 5;
6 is a gate insulating film provided on the p-type semiconductor substrate 1, 7 is a gate electrode provided on the gate insulating film 6, and 8 is a channel formed on the surface of the semiconductor substrate 1 between the source and drain.

Next, the operation of this MOSFET will be explained using a diagram showing the band structure between the source and drain.

Figures 4a and 4b are diagrams showing schematic band structures spanning the source region, semiconductor substrate surface, and drain region in Figure 3. Figure 4a is a band diagram in a thermal equilibrium state, and Figure 4b is a gate FIG. 7 is a band diagram when a positive voltage is applied to the electrode 7 and a channel 8 is formed between the source and drain. In FIGS. 4a and 4b, Ec is the conduction band edge, Ev is the filling band edge, and Ef is the Fermi level.

As shown in Figure 4a, when the gate voltage is 0V (thermal equilibrium state), there is a barrier due to a pn junction on the semiconductor substrate surface between the source and drain, so the voltage between the source and drain (drain voltage)
Even if the voltage is applied, electrons cannot move from the source region 2 to the drain region 4. On the other hand, when a positive voltage is applied to the gate electrode 7, electrons are induced on the surface of the semiconductor substrate, forming a channel (inversion layer), resulting in the band structure shown in FIG. 4b. In this state, there is no longer a barrier due to the pn junction on the surface of the semiconductor substrate between the source and drain, and electrons can easily move from the source region 2 to the drain region 4. In this way, in a MOSFET, the current between the source and drain (drain current) is controlled by the gate voltage.

(Problems to be Solved by the Invention) In the conventional MOSFET described above, in principle, the mutual conductance (change in drain current with respect to change in gate voltage) is simply proportional to gate voltage, so the load driving ability is small and high There is a problem in that high-speed operation is suppressed because the wiring capacitance increases and the delay rate due to driving an external load increases with integration. To solve this problem, it is necessary to strengthen the nonlinearity of the mutual conductance and increase the load driving ability, similar to bipolar transistors.

An object of the present invention is to provide a semiconductor device capable of ultra-high-speed operation.

(Means for Solving the Problems) A semiconductor device of the present invention is a semiconductor which is formed on a substrate made of a semiconductor or an insulator and which contains impurities of one conductivity type at a high concentration and is close to a degenerate state and in which no inversion layer is formed. a channel region consisting of a channel region, a source region and a drain region made of a degenerate semiconductor having high concentration impurities of opposite conductivity type formed on the substrate with the channel region sandwiched therebetween, and a gate insulating film provided on the surface of the channel region. , a gate electrode provided on the gate insulating film, and a source electrode and a drain electrode forming ohmic contact with the source region and the drain region, respectively.

(Function) In the semiconductor device of the present invention configured as described above, the drain current is controlled by changing the tunneling probability of carriers between the source and the channel region surface and between the channel region surface and the drain using the gate voltage. Since the tunneling probability changes as an exponential function of the potential difference and the pn junction depletion layer thickness, the mutual conductance has large nonlinearity.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of an embodiment of the present invention.

In FIG. 1, reference numeral 9 denotes a channel region made of a semiconductor layer that contains a high concentration of p-type impurity but has not reached degeneracy. Each layer in this example has an acceptor concentration of 5 as the p-type semiconductor substrate 1.
Si with a donor concentration of approximately ×10 ¹⁸ cm ^-3 as the n-type source region 2 and drain region 4, Al with a donor concentration of approximately 5 × 10 ¹⁹ cm ^-3 as the source electrode 3 and drain electrode 5, and a thickness as the gate insulating film 6. Thermal oxidation SiO ₂ with a thickness of about 100 Å, p-type polysilicon as the gate electrode 7, and Si with a thickness of about 200 Å and an acceptor concentration of about 1×10 ¹⁹ cm ^-3 as the p-type channel region 9 were used. Further, the distance between the source and drain is about 500 Å.

Next, the operation of this example will be explained in the second section showing the band structure.
This will be explained using figures.

2a and 2b are diagrams showing a schematic band structure extending from the source region 2 in FIG. 1 through the surface of the channel region 9 to the drain region 4, and FIG.
is a band diagram in a thermal equilibrium state, and FIG. 2b is a band diagram when a negative voltage is applied to the gate electrode to form a degenerate accumulation layer on the surface of the channel region.

In the thermal equilibrium state shown in Figure 2a, Si in the n-type source and drain regions and Si in the p-type channel region are
An electron barrier is formed between it and Si by a pn junction. Since the acceptor concentration in the channel region is not high enough to cause degeneracy, the width of this barrier is 100
The barrier is wide, more than Å, and there is almost no probability of tunneling through this barrier. Therefore, even if a minute voltage of about 0.1V is applied between the source and drain, almost no drain current flows.

On the other hand, when a negative voltage is applied to the gate electrode 7 to form a hole accumulation layer on the surface of the channel region as shown in FIG. 2b, the surface of the channel region 9 becomes a degenerate semiconductor. As a result, the width of the pn junction barrier between the source region and the drain region becomes extremely narrow (100 Å or less), and the probability of tunneling through this barrier increases. Then, a drain current starts to flow by applying a drain voltage. Since tunnel current changes exponentially with junction potential difference and depletion layer width, drain current and transconductance exhibit strong nonlinearity with respect to gate voltage. Furthermore, since the tunnel effect is the basic operating principle of this semiconductor device, the transit time of electrons is extremely short, less than 1 ps.

Next, a manufacturing method according to an embodiment of the present invention will be described.

First, a channel region 9 of approximately 200 Å is formed on the surface of a p-type semiconductor substrate 1 made of Si by molecular beam epitaxy.
deposit. Next, this surface is thermally oxidized to 100%
A gate insulating film 6 having a thickness of about .ANG. is formed, and polysilicon is deposited thereon by vapor phase growth and patterned to form a gate electrode 7.

Next, using gate electrode 7 as a mask, As ions are implanted into p-type semiconductor substrate 1 and annealed to form source region 2 and drain region 5. After that, a SiO ₂ film was deposited as a protective film by vapor phase epitaxy, and contact holes for the source region, drain region, and gate electrode were made there.
The semiconductor device is completed by depositing Al and shaping each electrode into the shape. As described above, the manufacturing method of this embodiment is very easy and suitable for high integration.

Although the above embodiments have been described with respect to a p-type channel region, it is clear that the present invention is equally applicable to an n-type channel region in which the conductivity types of the semiconductors in each region are reversed. Furthermore, although the semiconductor substrate and the channel region may have the same negative voltage concentration, it is preferable to lower the impurity concentration of the semiconductor substrate in order to increase the withstand voltage and reduce parasitic capacitance. Of course, an insulator may be used as the substrate.

Although only Si was shown as a semiconductor, C,
Group semiconductors such as Ge and SiC, GaAs, InP, InAs,
- Group compound semiconductors such as Gap, InGaAs, and InGaAsP, - group compound semiconductors such as CdTe and ZnTe, and other various semiconductors may be used. However, since the densities of states in the conduction band and charge band are different in each semiconductor, the concentration of impurities that cause degeneracy is different, and the source and drain regions of the present invention do not contain impurities at a high concentration that causes sufficient degeneration. It is necessary to contain it. In addition, insulators such as Si ₃ N ₄ and Al ₂ O ₃ other than SiO ₂ can also be used as the gate insulating film, or semiconductors with a wider forbidden band width than the semiconductors in the channel region (for example, AlGaAs versus GaAs) can be used. It is clear that it is possible.

(Effects of the Invention) As described above, the semiconductor device of the present invention has a structure suitable for integration and has a large load driving capability, so it has the advantage of being capable of ultra-high-speed operation.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an embodiment of the present invention, FIGS. 2a and b are a band diagram of the embodiment in FIG. 1 in a thermal equilibrium state and a band diagram when a negative voltage is applied to the gate electrode, and FIG. 3 is a cross-sectional view of an example of a conventional MOSFET,
4a and 4b are band diagrams of the MOSFET of FIG. 3 in a thermal equilibrium state and a band diagram when a positive voltage is applied to the gate electrode. DESCRIPTION OF SYMBOLS 1...p-type semiconductor substrate, 2...n-type source region, 3...source electrode, 4...n-type drain region, 5...drain electrode, 6...gate insulating film,
7... Gate electrode, 8... Channel, 9... P-type channel region, Ec... Conduction band edge, Ev... Filling band edge, Ef... Fermi level.

Claims (1)

[Claims] 1. A channel region formed on a substrate made of a semiconductor or an insulator and made of a semiconductor that contains impurities of one conductivity type at a high concentration and is in a degenerate state so that no inversion layer is formed, and a channel region formed on the substrate with the channel region sandwiched therebetween. a source region and a drain region made of a degenerate semiconductor containing highly concentrated impurities of opposite conductivity type; a gate electrode provided on the surface of the channel region; and a source forming ohmic contact with the source region and the drain region, respectively. A semiconductor device comprising an electrode and a drain electrode.