JPH0362303B2 - - Google Patents

Description

[Detailed description of the invention]

[Summary] The present invention provides a semiconductor device that uses interfacially quantized carriers, in which a heterojunction is formed between an In _x Ga _1-x As semiconductor layer and an In _x Ga _1-x P semiconductor layer, and the In _x By using the Ga _1-x P semiconductor layer as a carrier supply layer and the In _x Ga _1-x As semiconductor layer as a carrier channel, it is possible to increase carrier concentration and improve stability. [Industrial Application Field] The present invention relates to improvements in semiconductor devices, particularly compound semiconductor devices such as high electron mobility field effect transistors (HEMTs) that utilize interfacially quantized carriers. For example, in HEMT, the mobility of electrons is increased through spatial separation doping and quantization at the heterojunction interface, and there are strong expectations for it as a high-speed device, but improvements are still desired as described below. [Prior Art] As an example of a semiconductor device that achieves high carrier mobility through carrier quantization and spatial separation doping at a heterojunction interface, a schematic cross-sectional view and an energy band diagram of an example of a HEMT are shown in Figures 4a and 4a. Shown in b. The semiconductor device has a non-doped i-type GaAs channel layer 2 which serves as a buffer layer and a channel layer on a semi-insulating gallium arsenide (GaAs) substrate 21.
3, and an _n -type electron supply layer 24 made of aluminum gallium arsenide ( _Al A two-dimensional electron gas 26 is formed near the heterojunction interface. This two-dimensional electron gas 26 has almost no decrease in mobility due to impurity scattering, and the highest mobility is obtained at low temperatures, for example, about 77 K or lower, where lattice scattering is reduced. Source and drain electrodes 28 are provided on this semiconductor substrate.
A gate electrode 29 is provided, and the surface concentration of the two-dimensional electron gas 26 is controlled by the shot depletion layer formed by the gate electrode 29 to perform transistor operation. The mixed crystal ratio x of AlAs and GaAs in the Al _x Ga _1-x As layer 24, which is the electron supply layer of this HEMT, is selected by comparing and examining the mobility μn and the areal concentration Ns of the two-dimensional electron gas 26. , the mobility μn reaches its maximum when x=0.2 to 0.3, and from the surface concentration Ns, the i-type GaAs layer 23
It is desirable that the energy level difference between the conduction band and the conduction band is about 0.24 eV or more, therefore, x=about 0.30 or more. However, on the other hand, if the mixed crystal ratio x of Al _x Ga _1-x As is made larger than about 0.25, the doped Si
etc., form a deep donor level called a DX center. For this reason, even if the doping amount is increased, the surface concentration Ns of the two-dimensional electron gas 26 does not increase commensurately, and if infrared rays are incident at a temperature below about 200 K, electrons are excited from the DX center to the conduction band.
This shows a phenomenon such as PPC (persistent photo conductivity) in which conduction electrons do not fall to the donor level when light irradiation is stopped. Therefore, in the GaAs/AlGaAs HEMT described above, drain current, transfer conductance gm, etc. are restricted, and furthermore, these characteristics and threshold voltage V _th etc. exhibit large temperature dependence, reducing operational stability. . GaAs/AlGaAs system with such problems
In order to improve HEMT, the present applicant previously provided the following structure whose energy band diagram is shown in FIG. 4c in Japanese Patent Application No. 58-195579. The semiconductor device according to the invention has an electron supply layer 24A.
is formed from indium gallium phosphide (In _0.48 Ga _0.52 P). Since InGap does not form a DX center, it not only increases the surface concentration Ns of the two-dimensional electron gas 26 and improves operational stability, but also improves the stability of operation because it does not contain aluminum (Al) as a constituent element. Metal pyrolysis vapor phase growth (MO−
It also has the effect of improving chemical stability during and after the vapor phase growth process such as the CVD method. [Problems to be solved by the invention] The invention of the prior application has the above-mentioned effects, but improvements such as further increasing the surface concentration Ns of the two-dimensional electron gas have been promoted without sacrificing the advantages. ,
The aim is to improve the performance of HEMTs, which have high expectations as high-speed devices. [Means for solving the problem] The above problem is solved by using an indium gallium arsenide compound (In _x Ga _1-x As) semiconductor layer and an indium gallium phosphorous compound (In _x Ga _1-x P) semiconductor layer doped with impurities. This problem is solved by a semiconductor device according to the invention in which the In _x Ga _1-x As semiconductor layer is provided with a heterojunction with the In x Ga 1-x As semiconductor layer as a channel for interfacially quantized carriers. [Function] The In _x Ga _1-x As heterojunction used in the present invention is
For example, In _0.48 Ga _0.52 P to lattice match the former to GaAs
When the latter is In _0.15 Ga _0.85 As, ΔE _c =
0.32eV, In _0.48 Ga _0.52 P/GaAs of the prior invention
A conduction band energy level difference larger than ΔE _c = 0.2eV of the heterojunction is obtained, and the areal concentration of the two-dimensional electron gas is
An increase in Ns is achieved. Note that using In _x Ga _1-x As for the channel layer,
For example, on an indium phosphide (InP) substrate, In _x Ga _1-x As with x = about 0.53 is used as a channel layer, and InP is used as an electron supply layer (for example, JP-A-58-196057, JP-A-59-5675). ΔE _c =0.2 eV even in such a conventional example. However, In _x Ga _1-x As has a different lattice constant from GaAs, which is often used as _a substrate for semiconductor devices _{. x} The required number of 10mm As semiconductor layers as quantized carrier channels
In _x
A structure in which a Ga _1-x As semiconductor layer and an In _x Ga _1-x P semiconductor layer are grown with mutual lattice matching is used. [Example] The present invention will be specifically described below with reference to Examples. FIGS. 1a and 1b are a schematic cross-sectional view and an energy band diagram showing a first embodiment of the present invention. The semiconductor substrate in this example is a semi-insulating GaAs substrate 1
Above, an AlGaAs buffer layer 2, an InGaAs channel layer 3, an InGaP electron supply layer 4, and a GaAs layer 5 are formed by, for example, the MO-CVD method as described below.

[Table] In this example, the buffer layer 2 is an Al _x Ga _1-x As layer with x = about 0.2 to 0.3.
This is to obtain a high resistivity of about 10 ¹¹ Ωcm or more. Note that even if AlGaAs is used for this buffer layer 2, the above-mentioned problem does not occur because it is a non-doped high resistance layer. Also, the buffer layer 2 is made of GaAs or In _0.48
It is also possible to use Ga _0.52 P or the like, and in this case, the energy band thereof takes the shape illustrated by the broken line in FIG. 1b. In the configuration of this embodiment, the mixed crystal ratio x of the In _x Ga _1-x As channel layer 3 is selected to be, for example, 0.15 to 0.20, and the thickness is selected to be, for example, about 10 to 15 mm, taking into account the occurrence of crystal defects. If x is increased, the ΔEc between the In _0.48 Ga _0.52 P electron supply layer 4 and the In 0.48 Ga 0.52 P electron supply layer 4 is increased, but the difference in lattice constant from GaAs is also large, which limits the thickness. In this embodiment, these are set to values shown in the following data example, for example. Source and drain electrodes 8 are patterned using, for example, gold germanium/gold (AuGe/Au) on this semiconductor substrate, and heat treatment is performed to form an alloy region 8A at a depth that reaches the InGaAs channel layer 3. Further, a gate electrode 9 is provided on the GaAs layer 5 using, for example, Al. In this way, the gate electrode 9 is made of GaAs.
By providing the layer 5 on the In _0.48 Ga _0.52 P electron supply layer 4, a greater shot barrier height can be obtained than when providing the layer 4 on the In 0.48 Ga 0.52 P electron supply layer 4. FIG. 2 is a diagram showing the average values of the surface concentration Ns and the mobility μn of the two-dimensional electron gas 6 at temperatures of 300 K and 77 K for the semiconductor substrates of this example and the prior invention, and is a diagram showing the average values of the surface concentration Ns and the mobility μn of the two-dimensional electron gas 6, which were obtained by the MO-CVD method. The In _0.48 Ga _0.52 P electron supply layer 4 of each sample grown by
×10 ¹⁸ cm ^-3 and thickness 37 mm. In the embodiment of the present invention indicated by ▲ and △, the mixed crystal ratio x of the In _x Ga _1-x As channel layer 3 is 0.15, the thickness is 8.7 mm, and ■
In the embodiment shown by and □, the mixed crystal ratio x of the InGaAs channel layer 3 is 0.15, and the thickness is 17 mm. In addition, samples of the prior invention are indicated by ● and ○, ▲, ■, ● are 300K,
△, □, and ○ indicate 77K. From this data example, the surface concentration Ns of the two-dimensional electron gas 6 is
is clearly increased by the present invention, and if the impurity concentration of the In _0.48 Ga _0.52 P electron supply layer 4 is made higher than the 1×10 ¹⁸ cm ^-3 of this example, the surface concentration Ns
can be further increased. Note that the mobility μn is considered to be the same at room temperature of 300K. At low temperatures, the mobility μn tends to decrease as the surface concentration Ns increases, which is the same as the previously known fact.
The selection is made depending on the thickness of the In _x Ga _1-x As channel layer 3, etc. Further, FIG. 3 is a schematic sectional view showing a second embodiment of the present invention. The semiconductor substrate in this example is a semi-insulating GaAs substrate 1
1, an InGaAs layer 13 and an InGaP electron supply layer 14 having a superlattice structure, which also serve as a buffer layer and a channel layer, are formed by MO-CVD as described below.
A source and drain electrode 18 and a gate electrode 19 are provided.

〔Effect of the invention〕

As explained above, according to the present invention, in a semiconductor device in which a channel is a carrier quantized at an interface by a heterojunction, instability in operation can be eliminated;
It is further estimated that the carrier concentration will be increased, which will have a great effect on HEMTs, etc., which are expected to be used as high-speed devices.

[Brief explanation of drawings]

Fig. 1 is a schematic cross-sectional view and energy band diagram of the first embodiment, Fig. 2 is a diagram showing an example of the areal concentration and mobility of a two-dimensional electron gas, and Fig. 3 is a schematic cross-section of the second embodiment. 4 are a schematic cross-sectional view and an energy band diagram of a conventional example. In the figure, 1 and 11 are semi-insulating GaAs substrates,
2 is a non-doped AlGaAs buffer layer; 12 is a non-doped AlGaAs buffer layer;
Buffer layer of GaAs/InAs superlattice structure, 3, 13
is In _x Ga _1-x As channel layer, 4 and 14 are In _x Ga _1-x
P electron supply layer, 5 is a non-doped GaAs layer, 6,
16 is a two-dimensional electron gas, 8 and 18 are source and drain electrodes, and 9 and 19 are gate electrodes.

Claims (1)

[Claims] 1. A heterojunction between an indium gallium arsenide compound semiconductor layer and an impurity-doped indium gallium phosphorus compound semiconductor layer, and the indium gallium arsenide compound semiconductor layer is used as a channel of an interface quantized carrier. A semiconductor device characterized by: 2. A patent claim characterized in that the indium gallium arsenide compound semiconductor layer is provided between the third compound semiconductor layer and the indium gallium phosphorus compound semiconductor layer, both of which are lattice matched to a gallium arsenide compound single crystal. The semiconductor device according to item 1. 3. The indium gallium arsenide compound semiconductor layer and the indium gallium phosphorus compound semiconductor layer are formed on a gallium arsenide compound semiconductor substrate via a semiconductor device that reduces the difference in lattice constant, and the indium gallium arsenide compound semiconductor layer and the indium gallium phosphorus compound semiconductor layer 2. The semiconductor device according to claim 1, wherein the phosphorus compound semiconductor layer and the phosphorus compound semiconductor layer are mutually lattice matched.