JPH0362306B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit that integrates logic devices that can achieve low power consumption and high integration.

Conventional low-power logic devices are generally complementary ICs, that is, CMOS-structured ICs in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series between a power source V _DD and GND.
This CMOSIC utilizes low power performance to
Widely used in calculators, memory, etc. Figure 1 shows this CMOS inverter. 1 is P
2 represents an N-channel transistor. Also, FIG. 2 shows the structure of this CMOS. Create a P ^- well 4 in the N ^- substrate 3. After that, N ⁺ becomes the source and drain on the N channel side.
Create diffusion layers 5 and 6 or P ⁺ diffusion layers 7 and 8 on the P side,
Gate films 9 and 10 and gate electrodes 11 and 12 are formed. Also, the gate input VG and drain output VD are the first
Corresponds to the figure. As can be seen from this structure, two gate electrodes and two drain diffusion layers are required to form one gate stage. Therefore, it has two major drawbacks: low integration and low speed due to large parasitic capacitance. Therefore, if we take CMOS memory for example, its standby power is on the order of μw, and by backing up the battery, the memory can be made non-volatile and used as non-volatile RAM. Making this data non-volatile is a major factor in replacing conventional core memory in order to make devices more compact. On the other hand, unless the memory capacity and speed can be increased, it will not be possible to apply it to mainframe memory, which is mainly used in computers.
Therefore, this CMOS memory, which has extremely low standby power and low operating power, has poor integration and cannot be increased in capacity as mentioned above, and is slow in speed.
In the end, the scope of application is becoming narrower.

Therefore, an object of the present invention is to provide a logic device that uses low power like CMOSIC and has higher integration and higher speed than CMOS.

FIG. 3 shows a structure as a specific example for explaining the idea of the present invention. N ⁺ board 2
1, a P ^-- epi layer 22 is formed. Then normal P
Diffusion layers for the N ^- part 24 for the channel transistor (this is used as an interface part, etc., but may be removed if unnecessary) and the P ^- part 23 are formed.
The P ^- portion, which becomes the N-channel substrate, is biased to the ground potential GND by the P ⁺ diffusion 25. Also N ⁺
Diffusion 33 biases the entire substrate to a positive potential, _VDD . N ⁺ diffusion layers 29, 30 which become sources and drains on the N channel side, and P ⁺ diffusion layers 31, 32 and gate oxide films 35, 3 on the P channel side.
6. Gate electrodes 38 and 39 form a normal MOS transistor. Now, the device of the present invention has N ⁺ diffusion layers 28, 29, which form normal sources and drains,
It is composed of an N ⁺ diffusion layer 26 formed at the same time as 30 and 33, and an N ⁺ diffusion layer 27 formed deeper and separately. The gate film 34 and the gate electrode 37 control a normal N-channel conductive layer thereunder. Further, the deep N ⁺ diffusion layer 27 and the substrate 21 operate as a load portion of this N channel transistor via the P ^-- epi layer 22.

FIG. 4 is an enlarged view of this part, and the symbols are the same as in FIG. 3. The hatched line 43 is a depletion layer extending from the N ⁺ substrate 21 to the P ^-- epi layer 22 . If a positive potential is applied to the gate electrode 37 of the N-channel transistor, an inversion layer 45 is formed directly under the gate and the transistor is turned on.
The potential V _DN of the N ⁺ diffusion layer 26 is the same potential as the GND of the N ⁺ diffusion layer 28 serving as a source. At this time, since the N ⁺ diffusion layer has the same potential as the P ^-- layer and the P ^- layer serving as the substrate, the depletion layer 42 does not spread so much and becomes only the amount depending on the diffusion potential. However, since the concentration of the P ^-- layer is particularly low, the depletion layer is a little easier to spread than in the P ^-- layer. The spread length l _D of this depletion layer is expressed as (1) l _D = √2 ( _D + _DN・_B. Here, εsi is the dielectric constant V _D of silicon.
is the diffusion potential, V _DN is the potential between the N ⁺ , P ^- layer, and P ^-- layer,
g is the electric charge, and N _B is the concentration of the P ⁻ layer and P ^-- layer. If the gate of the N channel is set to GND and the channel is turned off, the deep N ⁺ diffusion layer is pulled toward the N ⁺ substrate 21 side due to a slight leak between the depletion layers 42 and 43 and approaches the V _DD potential. Then (1)
According to the formula, when V _D increases, the depletion layer length l _D increases, and the drain region in contact with the depletion layer 43 is cooperatively pulled toward V _DD by positive feedback, as shown by the broken line 44. The expansion and contraction of this depletion layer due to the drain potential acts as a load for this N-channel transistor. Since the P ^-- epilayer 22 has a very low concentration, a slight change in the drain region potential V _DN causes (1)
As can be seen from the equation, the depletion layer spread varies greatly. This is the reason why a P ^-- layer is used. If the diffusion depth and concentration can be sufficiently controlled, the structure shown in Figure 2, in which a P ^- well is diffused into an N ^- substrate like a normal CMOSIC, can be used as a deep layer. The same principle can be applied if only the drain diffusion layer is provided. Also normal
If we ignore the slight leakage in the N ⁺ diffusion layer alone,
The same applies to the structure shown in FIG. 2 without the P channel transistor. At this time, the diffusion layer of the P ^- well needs to be shallow.

FIG. 5 shows the load current characteristics of FIG. 4. If the drain potential V _DN is the same potential as the substrate, the depletion layer is connected, but the current value is naturally 0. Furthermore, the time-depletion layer where V _DN is at the same potential as the substrate's GND is far away, and the current I _DN is very small. As V _DN increases little by little, the depletion layer approaches and carriers begin to diffuse through it, causing the current to rise exponentially with respect to V _DN . In this way, a negative resistance characteristic is obtained as shown in the figure. a has a high substrate concentration, c
It gets lower the further you go. Also drain N ⁺ layer and substrate N ⁺
This characteristic also changes depending on the layer spacing. In order to stabilize the inverter characteristics shown in Figure 4, V _DN must be 0.
It is better to have slightly more I _DN than channel leak. Also, if the operating current is not required to be extremely low, it is effective to keep the depletion layer somewhat in contact when V _DN is 0, as shown in characteristic a, to increase the load current and increase the speed. .

FIG. 6 shows an embodiment of the present invention, in which the drain depletion layer is brought into contact with the V _DD side in a planar manner. A P ^- well 62 is formed in an N ^- substrate 61. After that, N ⁺ diffusion layers 63, 64, and 65 for source/drain and V _DD bias are formed. Thereafter, gate electrode films 59 and 66 and electrodes 60 and 67 are formed. The input of this inverter is electrode 67. If the N ⁺ diffusion layer 64 of the drain is at the GND potential, the depletion layer is shrunk as shown in 69 and is separated from the depletion layer 68 of the N ⁺ diffusion layer 63 . If V _DN
When approaching the V _DD potential, the drain depletion layer becomes like 70, contacts the depletion layer 68, and operates in the same manner as shown in FIG. At this time, the gate electrode 60 on the contact point of this depletion layer becomes GND and plays the role of pushing the depletion layer of the drain region and V _DD bias downward from the surface and ensuring control of the depletion layer.
It is not necessary if the characteristics shown in FIG. 5 can be realized. Furthermore, if the portion in contact with the depletion layer is formed with an extremely low concentration as shown in FIG. 4, the operation will be more stable. Naturally, even if the N type in the above example is replaced with a P type, and the P type is replaced with an N type semiconductor layer, the same operation will occur.

FIG. 7 shows a static random access memory (RAM) cell constructed using the logic device of the present invention. transistor 7
3 and 74 are N-channel active elements, and 71 and 72 are loads for controlling the depletion layer according to the present invention. 71 and 73, 72 and 74 constitute an inverter. Transistors 75 and 76 are transfer gates switched by the address line ADDRESS, and control data input/output to/from BIT.

FIG. 8 shows a diagram configuring a two transistor/cell static memory using a depletion layer controlled load. Conventional statics always had six elements, but the same characteristics can be obtained with one-third of them. In FIG. 5, the existence of two stable potentials (d) at the same current value is utilized. The transfer gate 81 switched by the ADDRESS line has a slight leakage between it and the substrate (GND potential). If this were a constant current, it would be a memory cell that statically, and with a very small current, stores whether it is a low potential or a high potential. This is an unprecedented static memory. In other words, a large number of cells can be accommodated on one chip, and the high degree of integration, which has been a problem with conventional static memories, can be easily achieved. Although the gate and source of transistor 82 are at the same potential, a small current (subthreshold current) flows through the surface to maintain the contents of the cell. Further, this current does not need to be a constant current, and a slight leak such as punch-through or juncture may be used, or a resistor such as polysilicon may be used.

The present invention realizes the role of a load at low power and high speed by controlling the depletion layer, and as described above, the degree of integration is significantly improved while maintaining the low power operation of CMOS. In addition, the device area for both drain output and gate input is reduced to nearly half that of CMOS, reducing parasitic capacitance and increasing speed. Therefore, the logic device according to the present invention is superior to conventional devices in all respects such as lower operating power, higher degree of integration, and higher speed.In particular, as can be seen from the previous example, in terms of memory capacity, large capacity, It has a tremendous effect in that it can achieve high speed.

[Brief explanation of drawings]

Figure 1 shows a conventional CMOS inverter, and Figure 2 shows its structure. FIG. 3 shows an example of the structure of a logical device according to the present invention. FIG. 4 is a partial diagram thereof, FIG. 5 is a load characteristic of the present invention, and FIG. 6 is another example of the present invention. FIGS. 7 and 8 show memory cells using the element of the present invention. 42, 43, 44, 68, 69, 70... depletion layer, 71, 72, 80... depletion layer control load.

Claims (1)

[Claims] 1. A substrate of a first conductivity type, a diffusion layer of a second conductivity type formed on the substrate, and a diffusion layer formed within the diffusion layer.
In a semiconductor integrated circuit comprising a MOS transistor, the MOS transistor has a gate electrode,
comprising a drain region and a source region to which a first potential is applied, a load region formed in the diffusion layer near the drain region and to which a second potential is applied; A first depletion layer is formed in the drain region, a second depletion layer is formed in the vicinity of the drain region, and the second depletion layer expands as the potential of the drain region changes from the first potential to the second potential. A semiconductor integrated circuit characterized in that the diffusion layer between the load region and the drain region is a load resistance whose current value changes according to the spread of the second depletion layer. 2 the second region formed near the drain region;
2. The semiconductor integrated circuit according to claim 1, wherein the depletion layer expands in response to changes in the potential of the drain region and comes into contact with the first depletion layer.