JPS6320023B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory capable of low power consumption and high integration.

Conventional low-power logic devices are generally complementary ICs, that is, CMOS-structured ICs in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series between a power supply V _DD and GND. This CMOS IC is widely used in watches, calculators, memories, etc. due to its low power performance.

FIG. 1 shows this CMOS inverter. 1 indicates a P-channel transistor, and 2 indicates an N-channel transistor. Also, Figure 2 shows this C
The structure of MOS is shown. P ^- well 4 in N ^- substrate 3
make. After that, N ⁺ diffusion layers 5 and 6, which become the source and drain on the N channel side, and P ⁺ diffusion layers 7 on the P side,
8, gate films 9, 10, gate electrodes 11,
form 12. Furthermore, the gate input VG and drain output VD correspond to those shown in FIG. As can be seen from this structure, two gate electrodes are required to form one gate stage.
Two drain diffusion layers are required. Therefore, it has two major drawbacks: low integration and low speed due to large parasitic capacitance. Therefore, for example, if we take a CMOS memory, its standby power is on the order of μw, and by backing up the battery, the memory can be made non-volatile and used as a non-volatile RAM.

Making this data non-volatile is a major factor in replacing conventional core memory in order to make devices more compact. On the other hand, unless the capacity and speed of the memory can be increased, it will not be possible to apply it to mainframe memory, which is mainly used in computers. Therefore, this CMOS memory, which has extremely low standby power and low operating power, has a low degree of integration and cannot be increased in capacity, as mentioned above, and is slow in speed, resulting in a narrow range of applications.

Accordingly, an object of the present invention is to provide a high-performance semiconductor memory that uses low power, high-integration, and high-speed logic devices unlike CMOS ICs.

FIG. 3 shows a structure as a specific example of the present invention. A P ^-- epi layer 22 is formed on an N ⁺ substrate 21 . Thereafter, a diffusion layer of an N ^- part 24 for a normal P channel transistor (this is used as an interface part, etc., but may be removed if unnecessary) and a P ^- part 23 are formed. The P ^- portion, which becomes the N-channel substrate, is biased to the ground potential GND by the P ⁺ diffusion 25. Furthermore, the entire substrate is biased to V _DD which is a positive potential due to the N ⁺ diffusion 33 .

N ⁺ which becomes the source and drain on the N channel side
Diffusions 29 and 30, P ⁺ diffusion layers 31 and 32 on the P channel side, gate oxide films 35 and 36, and gate electrodes 38 and 39 normally form a MOS transistor. Now, the device of the present invention has N ⁺ diffusion layers 28, 29, 30, 33 which form the normal source and drain.
It is composed of an N ⁺ diffusion layer 26 formed at the same time and an N ⁺ diffusion layer 27 formed deeper and separately.
The gate film 34 and the gate electrode 37 control a normal N-channel conductive layer thereunder. Further, the deep N ⁺ diffusion layer 27 and the substrate 21 operate as a load portion of this N channel transistor via the P ^-- epi layer 22.

FIG. 4 is an enlarged view of this part, and the symbols are the same as in FIG. 3. The shaded area 43 is a depletion layer extending from the N ⁺ substrate 21 to the P ⁻ epi layer 22 . If a positive potential is applied to the gate electrode 37 of the N-channel transistor, an inversion layer 45 is formed directly under the gate and it is turned on, and the drain N ⁺
The potential V _DN of the diffusion layer 26 is the same potential as the GND of the N ⁺ diffusion layer 28 serving as the source. At this time, the N ⁺ diffusion layer has the same potential as the P ^-- layer and the P ^- layer that serve as the substrate, so the depletion layer 4
2 does not spread that much and only depends on the diffusion potential. However, since the P ^-- layer has a particularly low concentration, the depletion layer is slightly
It spreads more easily than in the P ^- layer. The spread length l _D of this depletion layer is expressed as (1) l _D =√2( _D + _DN )・_B. Here, εsi is the dielectric constant of silicon V _D
is the diffusion potential, V _DN is the potential between the N ⁺ , P ^- layer, and P ^-- layer,
q is the charge, and N _B is the concentration of the P ⁻ layer and P ^-- layer.
If the gate of the N channel becomes GND and the channel is turned off, the deep N ⁺ diffusion layer becomes the depletion layer 42.
Due to the slight leak between and 43, N ⁺ substrate 2
1 side and approaches the V _DD potential. Then, according to equation (1), as V _D increases, the depletion layer length l _D increases and comes into contact with the depletion layer 43 as shown by the broken line 44. The drain is strongly pulled toward V _DD by positive feedback. The expansion and contraction of this depletion layer due to the drain potential is
It acts as a load for this N-channel transistor. Since the P ^-- epilayer 22 has a very low concentration, a slight change in the drain potential V _DN causes a large change in the spread of the depletion layer, as can be seen from equation (1). This is the reason for using the P ^-- layer, but if the diffusion depth and concentration can be sufficiently controlled, the structure shown in Figure 2, in which the P ^- well is diffused into the N ^- substrate like a normal C MOS IC, can be used. , the same principle can be applied if only a deep drain diffusion layer is provided. Also normal N ⁺
If you ignore minute leaks in the diffusion layer alone, the second
The same applies to the structure shown in the figure except that the P channel transistor is removed. At this time, the diffusion layer of the P ^- well needs to be shallow.

FIG. 5 shows the load current characteristics of FIG. 4. If the drain potential V _DN is the same potential as the substrate, the depletion layer is connected, but the current value is naturally 0. Also, the time-depletion layer where V _DN is at the same potential as the substrate's GND is far away, and the current I _DN is very small. As V _DN increases little by little, the depletion layer approaches and carriers begin to diffuse through it, causing the current to rise exponentially with respect to V _DN . In this way, a negative resistance characteristic as shown in the figure is obtained. The substrate concentration is high at point a, and becomes lower toward point c. This characteristic also changes depending on the distance between the drain N ⁺ layer and the substrate N ⁺ layer. In order to stabilize the characteristics of the inverter shown in FIG. 4, it is better to have I _DN slightly larger than the channel leakage when V _DN is 0. Also, if the operating current is not required to be extremely low, V _DN will be 0 as in characteristic a.
If the depletion layer is kept in contact with the depletion layer to some extent at this time, the load current can be considerably large, which is effective in increasing the speed.

FIG. 6 shows another example of application of the present invention, in which the drain depletion layer is brought into contact with the V _DD side in a planar manner. A P ^- well 62 is formed in an N ^- substrate 61. After that, N ⁺ diffusion layers 63, 64, and 65 for source, drain, and V _DD bias are formed.
Thereafter, gate films 59 and 66 and electrodes 60 and 67 are formed. The input of this inverter is electrode 67. If the N ⁺ diffusion layer 64 of the drain is at the GND potential, the depletion layer is shrunk as shown in 69 and is separated from the depletion layer 68 of the N ⁺ diffusion layer 63 . If V _DN
When approaching the V _DD potential, the drain depletion layer becomes like 70, contacts the depletion layer 68, and operates in the same manner as shown in FIG. At this time, the gate electrode 60 on the contact point of this depletion layer becomes GND, which plays the role of pushing the drain and V _DD bias depletion layer downward from the surface and ensuring control of the depletion layer.
It is not necessary if the characteristics shown in the figure can be achieved. Furthermore, if the portion in contact with the depletion layer is formed with an extremely low concentration as shown in FIG. 4, the operation will be more stable. Naturally, even if the N type in the above example is replaced with a P type, and the P type is replaced with an N type semiconductor layer, the same operation will occur.

FIG. 7 shows a static random access memory (RAM) cell constructed using the logic device of the present invention. transistor 7
3 and 74 are N-channel ACD elements, and 71 and 72 are loads for controlling the depletion layer according to the present invention. 71 and 73, 72 and 74 constitute an inverter. Transistors 75 and 76 are transfer gates switched by the address line ADDRESS, and control data input/output to/from BIT.

FIG. 8 shows a diagram configuring a two-transistor cell static memory using a depletion layer controlled load. Conventional statics always had six elements, but the same characteristics can be obtained with one-third of them. In FIG. 5, the existence of two stable potentials (d) at the same current value is utilized. The transfer gate 81 switched by the ADDRESS line has a slight leakage between it and the substrate (GND potential).
If this is a constant current, it is static,
What's more, it becomes a memory cell that memorizes whether the potential is low or high using a very small amount of current. This is an unprecedented static memory. In other words, a large number of cells can be accommodated on one chip, and the high degree of integration, which has been a problem with conventional static memories, can be easily achieved. Although the gate and source of transistor 82 are at the same potential, a small current (subthreshold current) flows through the surface to maintain the contents of the cell. Further, this current does not need to be a constant current, and a slight leak such as punch-through or juncture may be used, or a resistor such as polysilicon may be used.

FIG. 9 is an example in which the memory cell shown in FIG. 7 is patterned. polysilicon layers 102, 94,
95 is a diffusion region 91, 92, 93 surrounded by solid lines.
Configure the gate on top of. Al wiring 104,1
05, 106, 107 are x marks 96, 97, 10
0, 101 and diffusion regions 91, 92, 93, and ×
Contact is made to the polysilicon at marks 98 and 99. The diffusion region 91 is a source 92, 9 of GND potential.
3 is a drain. The area of this cell is 42μm×
28μm×60μm, N MOS960μm×40μm
This is a significant decrease compared to the previous year. 4th with this pattern
To describe an example of a prototype memory fabricated using the structure shown in the figure, the concentration of the P ^-- layer is approximately 5 x 10 ¹⁴ /cm ² , and the concentration of the P ^-- layer and
P ^-- layer thickness 11μm, N ⁺ depth 3μm, P ^- depth 4μm, formed by ion implantation. At this time, the standby power per cell is approximately 1 μW, and the operating speed for address access is approximately 150 msec.
This is slightly lower in power than traditional CMOS memory, but the speed is nearly three times faster.

FIG. 10 is an example in which the cells in FIG. 8 are patterned. The gate line 113 and the source diffusion layer 110 are
It has the same potential as GND. A depletion layer control memory section exists directly below the drain 111. gate line 11
4 controls the transfer gate. At step 115, a BIT made of Al wiring 116 is contacted in order to input and output cell data. This cell size is only 12 μm x 21 μm, which is only 5% of a conventional CMOS cell. Conversely, it is possible to achieve 20 times more memory capacity. This device can be manufactured similarly to the pattern of FIG. 9 described above. Furthermore, when transferring this cell, the impedance of the cell is lowered by biasing the gate line 113 to the + side, and the read access speed gradually increases.

The present invention realizes the role of a load at low power and high speed by controlling the depletion layer, and as described above, the degree of integration is significantly improved while maintaining the low power operation of CMOS. In addition, since the device area for both drain output and gate input is less than half that of CMOS, the parasitic capacitance is reduced to one-third due to the lower substrate concentration, resulting in a noticeable increase in speed. . Therefore, the logic device according to the present invention is superior to conventional devices in all respects, such as lower operating power, higher degree of integration, and higher speed.In particular, as can be seen from the previous example, memory capacity can be increased as can be seen by comparison. , it has a tremendous effect in that it can achieve high speed.

[Brief explanation of the drawing]

Figure 1 shows a conventional CMOS inverter; Figure 2 shows a conventional CMOS inverter;
The figure shows its structure. FIG. 3 shows an example of the structure of a logical device according to the present invention. Figure 4 is a partial diagram of the
FIG. 5 shows the load characteristics of the present invention, and FIG. 6 shows another example of the present invention. 7 and 8 show a memory cell using the device of the present invention. 9 and 10 show the patterns of FIGS. 8 and 9. FIG. 42, 43, 44, 68, 69, 70... Depletion layer, 71, 72, 80... Depletion layer control load.

Claims (1)

[Scope of Claims] 1. A first MOS transistor comprising a first region, a second region, and a gate electrode, and a transistor connected between the second region of the first MOS transistor and a bit line and connecting the gate electrode to an address line. 2nd MOS connected to
transistor, and a first potential is applied to a first region of the first MOS transistor.
forming a third region of a conductivity type, and forming the first MOS transistor in the third region,
A first depletion layer is formed near the junction region between the substrate and the third region, and the second region is formed near the second region of the first MOS transistor. A second depletion layer is formed that expands as the potential changes, and the memory cell extends the third region between the substrate and the second region of the first MOS transistor into the second depletion layer. A semiconductor memory characterized by a load resistance whose current value changes according to the spread of the current. 2 A first MOS transistor consisting of a first region, a second region and a gate electrode, and a second MOS transistor connected between the second region of the first MOS transistor and the bit line and having its gate electrode connected to the address line. M.O.S.
transistor, and a first potential is applied to a first region of the first MOS transistor.
A third region of a conductive type is formed, a fourth region to which the first MOS transistor and the second potential are applied is formed within the third region, and a fourth region is formed near the fourth region. 1 depletion layer is formed, and the first depletion layer
The second region of the MOS transistor is located near the second region of the MOS transistor.
A second depletion layer is formed that expands as the potential of the region changes from the first potential to the second potential, and the memory cell is formed between the fourth region and the first potential.
the third region between the second region of the MOS transistor;
A semiconductor memory characterized in that the region is a load resistance whose current value changes according to the spread of the second depletion layer.