JPH0362341B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a line scanning control method of a communication control processing device, a shared LCW memory is provided in which a line control word (LCW) shared for transmission and reception channels is stored; During each service period of the channel, each transmitting and receiving
Transmission and reception line scanning control is performed by referring to the shared LCW memory as well as the LCW memory. This results in
LCW memory can be used efficiently by reducing the number of LCW words.

[Industrial application field]

The present invention relates to a line scanning control method in a line adapter provided in a communication control processing device, and in particular, to reducing the number of line control words stored in a line control word memory without degrading the line scanning control function. This invention relates to a line scanning control method that enables efficient operation.

[Conventional technology]

The communication control processing device is interposed between the communication line and the host processor, and is equipped with a channel adapter, line adapter, central processing unit, etc., and is used between the host processor and other computer systems, terminal devices, etc. connected to the communication line. performs the necessary control when transmitting data.

At that time, the channel adapter controls data transfer between the host processor and the communication control processing device,
The line adapter controls data transmission and reception between the communication line and the communication control processing device, and the central processing unit has an internal control program (NCP: Network control
program), and controls overall communication control operations performed by the communication control processing device, including control of channel adapters and line adapters.

FIG. 5 is a block diagram showing the basic configuration of the line adapter.

In FIG. 5, 200 is a line adapter;
0 is a system bus within the communication control processing device.

In the line adapter 200, 210 is a control memory in which control programs and data for controlling the operation of the line adapter 200 are stored.

Reference numeral 220 denotes a line scanning unit, which includes a plurality of line control word memories (LCW memories) 221 ₁ to 221 _o , and controls line scanning and disassembly/assembly of transmitted and received characters. The LCW memories 221 ₁ to 221 _o each contain LCWs for transmitting channels and receiving channels.
There is a memory, the former storing the line control word (LCW) for the transmit channel, and the latter storing the LCW for the receive channel.

A line connecting device interface 230 performs interfacing and connection operations with a communication line.

A system bus control unit 240 interfaces between the system bus 300 and the line adapter 200, and controls the transfer of data and control information to and from a central processing unit (not shown).

250 is a processor (MPU) which is controlled by the control program stored in the control memory and runs the line scanning unit 220.
and controls the entire operation of the line adapter 220 including control of the system bus control unit 240.

[Problem that the invention seeks to solve]

In the line adapter of the conventional communication control processing device, as mentioned above, there is a
Separate LCW and receive channel LCW
It was stored in LCW memory and used to control line scanning during sending and receiving channel services.

However, since each LCW memory for the transmission and reception channels is built into a semiconductor chip, the scale of the LCW memory is currently limited to a small size and small capacity due to its structure.

For this reason, increasing the number of channels reduces the capacity of each LCW memory, reduces the number of line control words set in the LCW, and degrades the line scanning control function; conversely, increasing the number of line control words improves the line scanning function. However, the present invention reduces the number of LCW words stored in the LCW memory without degrading the line scanning control function, and reduces the number of LCW words stored in the LCW memory under the limited capacity. The purpose of the present invention is to provide a line scanning control method that enables efficient use of the line scanning control system.

[Means for solving problems]

The means taken by the present invention to solve the above-mentioned problems in the conventional line scanning system will be explained with reference to FIG.

FIG. 1 is a block diagram showing the basic configuration of the present invention.

In FIG. 1, 100 is a line scanning section of a line adapter, which corresponds to the line scanning section 220 in FIG.
Performs line scanning control.

Reference numeral 110 denotes a line control word memory means (LCW memory means) in which the LCW for the transmitting and receiving channels is stored, and is shared as the LCW for the transmitting and receiving channels together with the LCW for the transmitting or receiving channel.
Shared line control word memory (shared LCW memory) in which the LCW is stored and is accessible during both transmit channel and receive channel service periods.
It has at least one.

Reference numeral 120 denotes a scanning address control means, which generates a transmission channel address, a reception channel address, and a reception channel address of a line to be scanned next during a scan cycle for one line.

Reference numeral 130 denotes a line scanning control means, which uses the address generated by the scan address control means 120 during the transmission channel service period of the scan cycle.
ICW for transmit channel in LCW memory means 110
The memory and the shared LCW memory are accessed to perform transmission line scanning control, and during the reception channel service period, the reception channel LCW memory and the shared LCW memory in the LCW memory means 110 are accessed using the address generated by the scan address control means 120. to perform receiving circuit scanning control.

[Effect]

The line scanning control means 130 performs transmission channel service and reception channel service during the scan cycle of one line.

During the transmission service period, the LWM scan 11 is controlled by the address generated by the scan address control means 120.
Transmission line scanning control is performed while referring to the transmission channel LCW and shared LCW memory in 0.

During the reception service period, the LCW examination 11 is performed using the address generated by the scanning address control means 120.
LCW memory for receiving channels within 0 and shared LCW
Performs reception line scanning control by referring to memory.

As mentioned above, the shared
Since an LCW memory is provided and LCWs commonly used during the transmission channel service period and reception service period are stored in this shared LCW memory, the number of transmitting or receiving LCWs stored in the shared LCW memory is equal to the number of LCWs stored in the shared LCW memory. The number of LCW words stored in one side can be reduced. Therefore,
The number of LCW words stored in the LCW memory device 110 can be reduced and the LCW memory can be used efficiently.

〔Example〕

Embodiments of the present invention will be described with reference to FIGS. 2 to 4.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 3 is an explanatory diagram of an LCW memory including a shared LCW used in the embodiment, and FIG.
The figure is a time chart during full duplex scan operation of the same embodiment.

(A) Configuration of Embodiment In FIG. 2, a line scanning section 100, a line control word memory means (LCW memory means) 110,
The scan address control means 120 and the line scan control means 130 are as explained in FIG.

In the LCW memory means 110, 111-
115 is line control word memory (LCW memory),
A circuit control word (LCW) for a transmit channel or a receive channel is stored.

Reference numerals 116 to 118 denote shared line control word memories (shared LCW memories) in which the LCW for the transmission or reception channel and the LCW shared by both are stored. Each shared LCW memory 116 to 118 is
In this embodiment, a known 2-port random access memory (2-port RAM) is used.

2-port RAM can be accessed by two addresses (A system and B system (B ₀ to B ₂ )), and address A can be read and written, but address B can only be read. Na
It is RAM.

The scan address control means 120 uses a scan counter (not shown) to generate a transmission channel address n, a reception channel address (n+1), and a reception channel address (n+3) of the line to be scanned next. These addresses allow LCW memories 111 to 115 and the shared LCW
A system address (LCW address A) that accesses memories 116 to 118, and shared LCW1
It is used as a B-system address (LCW address _B0 to _B2 ) for accessing 16 to 118.
Note that since the LCW addresses A, B ₀ to B ₂ change during the transmission service period, reception service period, etc., the address value at each operation time is, for example, A.
(n), A(n+1) will be shown in parentheses (These LCWA, B ₀ to B ₂ will be explained in detail in the section (B) Operation of Example below) .

In the line scanning control means 130, reference numeral 131 is a data-in register, into which data or LCW from the adapter's processor (MPU) or control memory (none of which are shown) is transferred from the internal bus and set. 132 is a data out register in which data or LCW to be transferred to the control memory or the like of the MPU is set. 133 is a calculation section,
Calculations are performed based on data or information transferred from the data out register 132, the LCW memory means 110, and an external line connection device interface (not shown), and the results are transferred to the data out register 132, LCW
The data is transferred to the memory means 110 or to the line connection device interface. Reference numeral 134 denotes an internal timing control unit that generates internal timing (T ₀ to T ₁₁ , etc., see FIG. 4a) that defines the operations performed by each part within the line scanning unit 100. 135 and 136
is a receiver and driver for system bus connections.

Next, a specific example of the shared LCW memories 116 to 118 will be explained with reference to FIG.

Figure 3A shows an example of an LCW memory including a shared LCW in which a shared LCW is stored together with a transmitting LCW, and the synchronization pattern data stored in area 1 is stored at LCW address A and LCW address _B0 . It is accessed and utilized during both the sending and receiving channel service periods.

Figure 3B shows an example of an LCW memory including a shared LCW in which the common LCW is stored together with the receiving LCW, and the data of modem control 1 in area 3 is accessed by the LCW address and LCW address _B1 . and is used during both the transmit and receive channel service periods.

(B) Operation of the embodiment The operation of the embodiment will be explained with reference to the time chart in FIG. 4, taking the full-duplex scan system as an example. In FIG. 4a, T ₀ to T ₁₁ indicate internal timing.

In the full-duplex scan system, one line scan cycle (T ₀ to T ₁₁ ) is divided into a program cycle (T ₀ to _{T 3} ) and a scan cycle (T ₄ to T ₁₁ ), and the scan cycle is
It is further divided into a transmission cycle (T ₄ to T ₇ ) in which transmission channel service is performed and a reception cycle (T ₈ to T ₁₁ ) in which reception channel service is performed (FIGS. 4a and 4b).

In this scan cycle, the scan counter is initially n, and when n is set to a scan address (not shown), it counts up to (n+2) in the next scan cycle. The scan address register holds this value of n as a scan address during the scan cycle (FIG. 4c, d).

In addition, shared LCW memories 116 (LCW addresses are A and B 0 ) and 117 (LCW addresses are A and B ₀ ) and 117 (LCW addresses are A and B 0 )
and B ₃ ), the shared LCW is stored together with the receiving LCW (see Figure 3 B), and the shared LCW memory 11
5 (LCW address is A and B ₁ ) for sending
It is assumed that the LCW is stored (Fig. 3A
reference). The operation in each cycle will be explained separately below.

(B-1) Operation in Program Cycle In the program cycle (T ₀ to T ₃ ), the MPU of the line adapter accesses the LCW memory in the LCW memory device 110 .

The MPU and line scanning control means 130 perform read cycle R during this program cycle.
In the write cycle W, the LCW in the LCW memory area of the desired address (m) is read, and in the write cycle W, the LCW is written in the LCW memory area of the desired address (m) to the line scanning unit 100. The LCW address A(m) for accessing the LCW memory area is supplied by the scan address control unit 120.

(B-2) Operation in transmission In the transmission cycle (T ₄ to T ₇ ), transmission channel service is performed. During the transmission cycle, the scan counter is set to (n+2), and the scan address and register hold the scan address n (see Figure 4c,
e). Furthermore, scan address control means 120
generates n as LCW address A,
Generate n ₁ as LCW address B ₀ and (n+1) as B ₁ and B ₂ (FIG. 4 g to i).

In the read cycle R during the transmission cycle, the calculation unit 133 accesses the desired transmission LCW memory using the LCW address A(n), and accesses the shared LCW memory 117 using the LCW address B ₁ (n+1). Access (Figure 4 e-j.

The shared LCW memory 117 has a configuration as shown in FIG. 3B, and reads the contents of the modem control 1 and detects changes in the modem status, for example, when the clear-to-send signal CS sent from the modem changes from off to on. By detecting this, an instruction to start transmission is created. In response to this transmission start instruction, line data out information is transferred to the line connecting device interface at internal timings T ₆ and T ₇ (FIG. 4 a, m, n).

(B-3) Operation in reception cycle In the reception cycle (T ₈ to T ₁₁ ), reception channel service is performed. During the receive cycle, the scan counter is set to (n+2) and the scan address register holds scan address n (Figure 4c,
d). Furthermore, the scan address control unit 120
Generate (n+1) as LCW address A,
LCW address B ₀ as n, B ₁ as (n+
1), (n+3) is generated as B ₂ (Fig. 4 g to i).

In the read cycle R during the receive cycle, the calculation unit 133 calculates the LCW address A(n+
1), the desired receiving LCW memory is accessed, and the shared LCW memory 116 is accessed using the LCW address B ₀ (n) (FIG. 4 e to j).

The shared LCW memory 116 has a configuration as shown in FIG. 3A, and a synchronization pattern is stored in area 1.

BSC (Binary synchronous
communication) procedure, a synchronization pattern is required as a standard for monitoring the synchronization pattern of received data, but this standard agreement pattern is
This can be obtained by reading out the 6 synchronization patterns. Note that this synchronization pattern is incorporated into transmission data during transmission channel service.

In addition, the calculation unit 133 calculates the LCW address B ₂ (n+
3) accesses the shared LCW memory 118 and accesses its physical line address area (Fig. 3B).
(reference)), that is, the line address (N
+3) and set in the line address register (not shown). This line address (N+3) has internal timing T ₁₀ and
At _T11 , the data is transferred to the line connection equipment interface (Fig. 4 k-l). Note that the line address (N
+1) was set at the internal timing (T ₁₀ ', T ₁₁ ') of the previous scan cycle.

When the line connecting device interface receives this line address (N+3), it starts scanning the next line.

Although the embodiment for the full-duplex scan method has been described above, the present invention is not limited to this embodiment, and can also be used for the half-duplex scan method.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(b) By sharing the line control word LCW during each service period of the transmitting and receiving channels, the number of line control words can be reduced without degrading the line scanning control function.

(b) According to (a) above, if the number of line control words is the same, the capacity of the line control word memory can be decreased, and if the capacity of the line control word memory is the same, the number of channels can be increased or the number of line control words can be decreased. The line control function can be improved by increasing the number of lines.

[Brief explanation of drawings]

Fig. 1...Explanatory diagram of the basic configuration of the present invention, Fig. 2...Explanatory diagram of the configuration of an embodiment of the present invention, Fig. 3...
...An explanatory diagram of the line control word memory including the shared line control word used in the same embodiment, Fig. 4...A time chart during full-duplex scan operation of the same embodiment, Fig. 5...Basic configuration of the line adapter An explanatory diagram. 1 and 2, 100... line scanning unit, 110... line control word (LCW) memory means, 120... scan address control means, 13
0...Line scanning control means.

Claims (1)

[Scope of Claims] 1. In a line scanning control method of a line adapter provided in a communication control processing device, (a) a line control word that is shared as a line control word for transmitting and receiving channels together with a line control word for a transmitting channel or a receiving channel; Line control word memory means for storing transmit and receive channel line control words, comprising at least one shared line control word memory in which a line control word is stored and is accessible during both the transmit and receive channel service periods. 110; (b) during a scan cycle for one line;
scan address control means 120 that generates a transmission channel address, a reception channel address of the line, and a reception channel address of the line to be scanned next; (c) during the transmission channel service period of the scan cycle, the scan address control means 120; Using the generated address, the transmission channel line word memory and the shared line control word memory in the line control word memory means 110 are accessed to perform transmission line scanning control, and during the reception channel service period, the scan address control means 120 generates The line control word memory means 1 according to the address
1. A line scanning control method, comprising: a line scanning control means 130 that performs receiving line scanning control by accessing a receiving channel line control word memory and a shared line control word memory in the receiving channel 10. 2. The line scanning control system according to claim 1, wherein the shared line control word memory is comprised of a 2-port random access memory.