JPH0362550A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor integrated circuit devices [(IC, LSI),
The present invention relates to a technology for reducing noise generation due to output ground current and rise in ground potential/output level in a gate array.

[Conventional technology]

On the main surface of the semiconductor substrate (chip), a plurality of input/output buffer areas are wired adjacent to each other as interfaces surrounding the internal logic cell V, and external pads (TL) are connected to these power supply, ground main lines, and buffer areas. A semiconductor multiplication circuit device in which a bonding pad (bonding pad) is formed is described in Nikkei Electronics June 3, 1985 issue, pages 151 to 177.

In such a semiconductor device, when driving a system with a large load, it is necessary to increase the driving performance of the LSI output, and for this purpose, two or more output cells (buffers) are connected in parallel and integrated into one. It is possible to take measures.

However, as the drive capacity has increased, the current flowing through the ground main line (ground current) when the outputs are simultaneously turned on has also increased by 2.
This will generate more than twice as much noise.

Furthermore, due to a large amount of current flowing through the ground, the output level fluctuates depending on the impedance component of the ground.

As one means of suppressing such noise generated in the ground, conventionally, it has been used to reinforce the ground by using it in the ground such as a buffer cell.

[Problem to be solved by the invention]

According to the above-mentioned conventional technology, by using unused input/output cells as a ground, the number of cells that can be used in the entire LSI is reduced, thereby increasing the efficiency of the semiconductor chip. There were 5 problems with using C.

The present invention is intended to solve the above-mentioned problems, and its purpose is to provide a semiconductor integrated circuit device that can reduce ground impedance by reinforcing the ground impedance that can be used on the surface of a semiconductor chip. It is in.

[Means for solving problems]

In order to solve the above object, the present invention provides a semiconductor device that has a plurality of input/output buffer areas along the periphery of a substrate, and has power supply lines, ground main lines, and external pads paired with each buffer area. In, 41 power sources,
The output ground trunk line is wired at the outermost periphery of the ground trunk line, and this ground trunk line is connected to a vacant external pad to be used as a ground.

[Effect]

By connecting the output ground main line wired on the outermost periphery to the empty pad and using it as a ground, noise is absorbed at the point closest to the output terminal, and at the same time, impedance can be reduced, and the entire LSI This improves the noise margin and suppresses output level fluctuations.
Furthermore, by using the empty pad Y, the chip area can be used effectively.

〔Example〕

Hereinafter, an embodiment in which the present invention is applied to a kegate array in an LSI will be described with reference to FIG. tfi.

FIG. 1 is a schematic plan view of the entire LSI. 1 is a semiconductor chip (substrate), and an internal logic cell group 2 is formed in the center of its main surface. i! Multiple input/output buffer areas 3 surround a group of buried cells 2 and serve as an interface.
are arranged adjacent to each other, and are interconnected on their surfaces by single-layer or multi-layer AJ (aluminum) wiring to form an LSI circuit. M wirings 4, 5, and 6 for power supply and ground main lines are wired above the buffer region via an interlayer insulating film. External pads (bonding pads) 7 are provided over the periphery of the chip so as to correspond to the buffer region.

In the present invention, two of the power supply and ground main lines are wired to the output ground 6'1 on the outermost periphery.

FIG. 2 is a partially enlarged plan view of the vicinity of the input/output buffer cell in the first cause. FIGS. 3 and 4 are cutaway diagrams of the ZM Nickel h-A:, B-B".

As shown in the same section, the external terminal (pad) 7 and the buffer cell 3 are connected via the lower layer AAtllill-, and the system ground is connected from the ground line pad 7g to the A1 layer 8 and the contact portion 9.10. The structure is connected to an external interface circuit (buffer cell).

Among these, two adjacent output cells 3a.

When connecting to one output pad 7a through A control #M8a of 3bv#A and using it as a single line (Fig. 3), the ground line 6 has an impedance due to the long distance to the ground line pad 7g. However, in the present invention, another pad 7b created by the common A1 wiring 8a connection is used, and as shown in FIG. By connecting to the outermost ground main line 6, the external pad 7b
Like the r-pad 7g, it is used as a system ground (for this purpose, it is placed at the outermost periphery of the ground trunk iv).

With this structure, when two or more output cells are used together, it is possible to significantly reduce the ground impedance, improve the noise margin, and stabilize the output level. have

〔Effect of the invention〕

According to the present invention described in the embodiments above, the following effects are achieved.

When a plurality of output cells are connected in parallel and used, the ground impedance of the output circuit that generates excessive noise can be reduced, and the noise margin of the entire LSI can be improved.

For this reason, the width of the ground trunk line is not increased, and since empty pads can be used, the number of input/output buffers that can be used is less variable, and the chip area can be used more efficiently.

[Brief explanation of drawings]

The first section is an overall schematic plan view of the LSI. FIG. 2 is a partially enlarged plan view of FIG. 1. FIG. 3 is a sectional view taken along the line AA' in FIG. 1, and FIG. 4 is a sectional view taken along the line <B-13'. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate (chip), 2... Internal logic cell group, 3*3a*3b... Input/output buffer area (interface circuit), 4... Power supply/ground trunk line, 5...
・Power/ground main line, 6... Output ground main line, 7.7at7b, 7g"・External pad, 8.8a...
・AA wiring tit, 9. 10... contact part,
11...A1 layout* T2+. Figure 8-A

Claims (1)

[Claims] 1. A plurality of input/output buffer areas are formed adjacent to each other along the periphery on one main surface of a semiconductor substrate, and are paired with these power supply lines, ground main lines, and each buffer area. A semiconductor integrated circuit device in which external pads are formed, in which a part of a plurality of input/output buffer areas is made up of two or more output cells connected in parallel, and their common terminals are connected to one external pad. In addition, a semiconductor integrated circuit device characterized in that an output ground main line wired at the outermost periphery of a plurality of power supply and ground main lines is connected to another vacant external pad for use as a ground. 2. In the semiconductor integrated circuit device according to claim 1, 2.
The parallel connection terminals of the three or more output cells and one external pad are connected by a lower layer aluminum wiring, and the connection between the outermost circumferential ground main line and another vacant external pad is connected by an upper layer aluminum wiring.