JPH0364045A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device, and is particularly effective when applied to a semiconductor integrated circuit device such as a B1-CMOS gate array. It is related to technology.

[Prior art] Regarding B1-CMOS gate array technology, see, for example, "Nikkei Electronics J, August 2, 1985, p.
7 to p. 208.

By the way, in a semi-custom semiconductor integrated circuit device such as such a gate array, a configuration has been considered in which a plurality of I/O cells and external pads are each in a one-to-one correspondence.

FIG. 2 shows an example of a semiconductor integrated circuit device including a plurality of I/O cells and external pads in one-to-one correspondence.

In the figure, reference numeral 3 indicates an internal circuit composed of a gate array, and this internal circuit 3 includes a Bi-CMOS
Circuits etc. are formed. Reference numeral 1 indicates an external pad connected to a lead not shown, and 2 indicates a work/○ cell (external interface circuit).
The cells 2, 2-2 and the external pads 1.1-1 are arranged in one-to-one correspondence, respectively. The external pads 1 and I
The I/O cell 2 is connected to the I/O cell 2 by a wiring 4 made of aluminum or the like, and a ground line 6 shown by a broken line is formed on the I/O cell 2. The I/O cell 2 and this ground line 6 are connected by a contact part /O, and a ground line contact 9 is provided on the ground line 6.
91 parts 8 are formed. This ground line connector 991 portion 8 is connected to the ground line external pad 7 which is connected to the ground potential (forms the ground potential) via the wiring 4a.

Therefore, when the above cell 2 is driven, the current is I/O
From cell 2 to contact part/O, ground line 6, ground line contact 1 part 8. It flows through the wiring 4a to the ground line external pad 7, and flows out to the external ground potential.

Recently, pass lines and the like that impose a large load have been connected to the external pad 1, and it has become necessary to increase the opening force.

Therefore, as shown on the right side of FIG. 2, one external pad 1a has two or more I/O cells (two or more I/O cells in FIG.
Attempts have been made to increase the driving force by connecting the motors 2 and 2a with parallel wiring 5 to increase the output.

[Problems to be Solved by the Invention] However, the above semiconductor integrated circuit device has the following problems.

In other words, a steep current flows from the I/O cells 2 and 2a, which are integrated in order to increase the opening force, toward the ground line external pad 7, and the ground impedance (inductance component + resistance component) increases. There are some problems. In particular, the distance between the contact part /O for the ground line 6 on the integrated I/O cells 2 and 2a and the ground line contact part 8 connected to the external pad 7 for the ground line is as shown in FIG. If the line is long as shown in , the inductance and resistance components will increase in proportion to the distance, which will generate large noise in the ground line 6 and cause the ground potential to float (rise). )
Normal operation cannot be expected.

Here, it is possible to solve the above problem by slowing down the speed of the current to prevent a steep current from flowing into the ground line external pad 7.

Since the high-speed performance is deteriorated, this is not preferable particularly for semiconductor integrated circuit devices including Bi-0M08 circuits.

The present invention has been developed in view of the above problems, and is capable of increasing the driving force while maintaining high speed, and at the same time, can reduce noise in the ground line and prevent floating of the ground potential. It is an object of the present invention to provide a semiconductor integrated circuit device that prevents this problem and enables normal operation.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, in a semiconductor integrated circuit device that includes a plurality of I/O cells and external pads in one-to-one correspondence, when two or more I/O cells are connected in parallel to one external pad, the 5-branch side A vacant pad corresponding to an I/O cell and a ground line to which the ground side of each I/O cell is connected are connected to shorten the length, and the potential of the vacant pad is set to the ground potential. be.

[Function] According to the above means, when two or more I/O cells are connected in parallel to one external pad, the I/O cells on the branch side
The empty pad corresponding to the O cell and the ground line to which the ground side of each I/O cell is connected are connected to shorten the length, and the potential of the empty pad is set to the ground potential, which improves high speed. Even if the opening force is increased while maintaining the current, the steep current from the negative I/O cell flows to this branch ground potential, and the ground impedance can be reduced, so the high speed is maintained. The above objectives of increasing the driving force, reducing noise in the ground line, and preventing floating of the ground potential to enable normal operation are achieved.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a semiconductor integrated circuit device according to the present invention. The outline is as follows.

In the figure, reference numeral 3 indicates an internal circuit composed of a gate array, and this internal circuit 3 includes Bi-0M08
Circuits etc. are formed. Reference numeral 1 indicates an external pad connected to a lead (not shown), and 2 indicates an I/O cell (external interface circuit).
The O cells 2, 2-2 and the external pads 1, 1-1 are arranged in a one-to-one correspondence, respectively. The external pad 1 and the I/O cell 2 are connected by a wiring 4 made of aluminum or the like, and a ground line 6 shown by a broken line is formed on the I/O cell 2. The I/O cell 2 and this ground line 6 are connected by a contact part /O, and a ground line contact 1 part 8 is formed on the ground line 6. This ground line contact 1 part 8 is connected to the ground line external pad 7 which is connected to the ground potential (forms the ground potential) via the wiring 4a. On the other hand, on the right side of the figure, 11! Two I/O cells 2, 2a are connected to one external pad 1a by a parallel wiring 5 in order to increase power. The ground line 6 on the I/O cell 2a on this branch side has an additional ground line capacitor 991/Oa.
is formed, and this additional connector 99 for the ground line
The first part /Oa is connected to the empty pad lla corresponding to the first part /O cell 2a via a wiring 9 made of aluminum or the like. This empty pad lla is connected to a ground potential (not shown), and its potential is the same as the ground potential.

Therefore, the steep current from the integrated I/O cells 2, 2a flows through the contact portion /O, the ground line 6, and the additional ground line ground line ground line ground line 9 near the integrated I/O cells 2, 2a.
91/Oa, most of it flows to the empty pad lla through the wiring 9 and flows out to the external ground potential, and almost no current flows to the conventional ground line external pad 7 side.

Here, in this embodiment, a contact part /O for the ground line 6 on the I/O cells 2 and 2a integrated to increase the driving force, and an additional ground line contact part 991 connected to the vacant pad lla. /Oa is extremely short, and the inductance and resistance components are made as small as possible, so the integrated I
Even if a steep current is generated from the /O cells 2, 2a, noise in the ground line 6 is suppressed to a low level, and floating of the ground potential is also prevented.

Note that in this embodiment, in order to increase the power a,
Although two I/O cells 2.2a are connected to one external pad 1a by parallel wiring 5, in this embodiment three or more I/O cells are connected to one external pad. It is equally applicable in cases where:
All the empty pads corresponding to the I/O cells on the branch side and the ground line 6 to which the ground side of each 1/O cell is connected are connected to shorten the length, and all the empty pads are connected to the ground potential. You can do it like this.

Only some of the empty pads may be connected to the ground line 6 to which the ground side of each I/O cell is connected in order to shorten the length.

According to the semiconductor integrated circuit device configured in this manner, the following effects can be obtained.

That is, when connecting two or more I/O cells 2 in parallel to one external pad 1a, the vacant pad lla corresponding to the I/O cell 2a on the branch side and the ground side of each I/O cell 2 The connected ground line 6 is connected to shorten the length, and the potential of the empty pad lla is set to the ground potential, so even if the driving force is increased while maintaining high speed, the integrated The steep current from the work/○ cells 2 and 2a immediately flows to the ground potential via the pad lla corresponding to the work/○ cell 2a on this branch side, and the ground impedance can be reduced, thereby maintaining high speed. It is possible to increase the driving force while maintaining the ground voltage, and at the same time, it is possible to reduce noise in the ground line 6, and to prevent floating of the ground potential, so that normal operation can be performed.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, although the above embodiment describes an example of application to a semiconductor integrated circuit device configured with a gate array, this embodiment is applicable to all semi-custom type semiconductor integrated circuit devices. In short, multiple I/
The present invention is applicable to all semiconductor integrated circuit devices in which O cells and external pads are in one-to-one correspondence.

Note that this embodiment maintains high speed, so Bi
-It is particularly effective when applied to a semiconductor integrated circuit device that includes a CMO5 circuit, but it is also applicable to a semiconductor integrated circuit device that is configured from a bipolar transistor that does not include a CMOS transistor or a CMOS transistor that does not include a bipolar transistor. can.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in a semiconductor integrated circuit device that includes a plurality of I/O cells and external pads corresponding to l pair (), when two or more I/O cells are connected in parallel to one external pad, The empty pad corresponding to the I/O cell and the ground line to which the ground side of each work/○ cell is connected are connected to shorten the length, and the potential of the empty pad is set to the ground potential, so high speed Even if the driving force is increased while maintaining the characteristics, the steep current from the integrated I/O cell will immediately flow to the ground potential via the pad corresponding to the I/O cell on the branch side. The ground impedance can be reduced.As a result, it is possible to increase the driving force while maintaining high speed, and at the same time, it is possible to reduce noise on the ground line, and also to reduce the floating ground potential. is prevented and normal operation is possible.

[Brief explanation of drawings]

FIG. 1 is a plan view of a main part of an embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a plan view of a main part of a semiconductor integrated circuit device conceived prior to the present invention. 1. External pad, la... 2 or more I/Os
External pad connected to the cell, 2... I/O cell,
2a...I/O cell on branch side, 5...Parallel wiring, 6...Ground line, 9...Connection wiring between empty pad and ground line, lla...Empty pad.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device including a plurality of I/O cells and external pads in one-to-one correspondence, two or more I/O cells are connected in parallel to one external pad. In case,
The empty pad corresponding to the I/O cell on the branch side and each of the I/O cells
A semiconductor integrated circuit device characterized in that the ground side of the O cell is connected to a ground line to which the ground side is connected to shorten the length, and the potential of the vacant pad is set to the ground potential. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device includes a Bi-CMOS circuit. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein a gate array is formed in the semiconductor integrated circuit device.