JPH0362565A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPH0362565A JPH0362565A JP19656589A JP19656589A JPH0362565A JP H0362565 A JPH0362565 A JP H0362565A JP 19656589 A JP19656589 A JP 19656589A JP 19656589 A JP19656589 A JP 19656589A JP H0362565 A JPH0362565 A JP H0362565A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- semiconductor device
- surface electrode
- conductive region
- resistance value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
本発明は半導体装置に係り、特に半導体基体との電気的
接続を行なうにあたり、微細で抵抗値の低い構造を提供
するものである。The present invention relates to a semiconductor device, and particularly to providing a fine structure with a low resistance value for electrical connection with a semiconductor substrate.
従来装置の一例を第２図に示す。第２図は特開昭６１−
１５０２６７号に記載されている図を引用したもので、
半導体基体端子の断面構造図を示したものである。
酸化膜１０上の多結晶Ｓｉ８が単結晶Ｓｉ７の側壁に接
して設けられる。多結晶Ｓｉ８は半導体基体１および高
濃度層６と同型導電形の高濃度不純物を含む６５は多結
晶Ｓｉ８から、不純物の拡散により形成される高濃度領
域である。表面電極２は多結晶Ｓｉ８、高濃度領域５．
６を通して半導体基体１と電気的に接続される。
この従来装置では、高濃度領域５，６に比べて多結晶Ｓ
ｉ８の抵抗率が低いため、特開昭６１−１５０２６７号
に述べられているように高濃度領域のみで半導体基体１
と表面電極２の電気的接続を行なう場合に比べ、小さい
領域で抵抗値を低く構成できる特徴があった。基本構造
は、高抵抗な第１・領域の周辺に低抵抗な第２領域を形
成した２重構造である。第２領域の抵抗率が第１領域の
抵抗率より十分に小さければ、半導体基体ｌと表面電極
２間の抵抗値はほぼ第２領域の抵抗値で決まる。
ところで、高周波帯域で用いる半導体装置においては、
半導体表面付近に設けたトランジスタ等の回路素子と半
導体基体間に生じる寄生容量の影響が大きくなる。この
寄生容量の低減が重要であると共に、寄生容量の安定性
も重要となる。半導体装置において上記の寄生容量には
電圧依存性があるため、寄生容量の安定性を得るために
は半導体基体の電位を一定にする必要がある。そのため
上述の従来例のように、半導体基体と表面電極を電気的
に接続して半導体基体の電位を一定にするここで、半導
体基体の電位を均一にするためには、半導体基体と表面
電極間の抵抗値を小さくしなければならない。
また、上記寄生容量を通して高周波信号電流が半導体基
体に誘起されると、この誘起高周波信号ｆｆｌ流により
、素子ならびに回路間のクロストークが生じる。クロス
トークの発生を低減するためには、上記の誘起高周波電
流をその発生源近傍で吸収する手段が取られる。その手
段は上述の寄生容量に対する方法と同様であり、半導体
基体と表面電極を電気的に接続し、表面電極を一定の電
位に保つことである。その効果は半導体載体と表面電極
間の抵抗値を小さいほど大きい。
前述した従来例の半導体装置によれば半導体基体と表面
電極間の抵抗を低減できる。すなわち高周波帯域で使用
する半導体装置の設計に際して、回路間の容量結合等に
悪影響を与えない範囲内で、半導体基体と表面電極との
電気的接続領域を極力広く設ける手法が用いられている
。
千り明が解決しようとする課題】
上記従来技術は、半導体基体と表面電極との電気的接続
部を２重構造とし、周辺の低抵抗な第２領域によって抵
抗値を低くするものである。従って、開口部の周辺長に
ほぼ等しい第２領域の周辺長によって抵抗値が定まる。
そのため、例えば。
開口部の面積を比例的に２倍にしても、周辺長は７２倍
にしかならず、抵抗値はほぼ０．７倍、すなわち約３０
％の低減に留まる。本発明の目的は。
従来技術の応用として表面電極の面積を広げずに半導体
基体と表面電極間の抵抗値を低減する構造を提供するこ
とにある。An example of a conventional device is shown in FIG. Figure 2 is JP-A-61-
This is a quotation from the figure described in No. 150267,
2 is a cross-sectional structural diagram of a semiconductor substrate terminal. Polycrystalline Si 8 on oxide film 10 is provided in contact with the sidewall of single crystal Si 7. The polycrystalline Si 8 contains a highly concentrated impurity having the same conductivity type as the semiconductor substrate 1 and the highly concentrated layer 6. Reference numeral 65 is a highly concentrated region formed from the polycrystalline Si 8 by diffusion of impurities. The surface electrode 2 is made of polycrystalline Si8, high concentration region 5.
It is electrically connected to the semiconductor substrate 1 through 6. In this conventional device, compared to the high concentration regions 5 and 6, polycrystalline S
Because the resistivity of i8 is low, the semiconductor substrate 1 can be removed only in the high concentration region as described in JP-A-61-150267.
Compared to the case where electrical connection is made between the surface electrode 2 and the surface electrode 2, the resistance value can be lowered in a smaller area. The basic structure is a double structure in which a low resistance second region is formed around a high resistance first region. If the resistivity of the second region is sufficiently smaller than the resistivity of the first region, the resistance value between the semiconductor substrate l and the surface electrode 2 is determined approximately by the resistance value of the second region. By the way, in semiconductor devices used in high frequency bands,
The influence of parasitic capacitance generated between a circuit element such as a transistor provided near the semiconductor surface and the semiconductor substrate increases. Not only is it important to reduce this parasitic capacitance, but also the stability of the parasitic capacitance is important. In a semiconductor device, the above-mentioned parasitic capacitance has voltage dependence, so in order to obtain stability of the parasitic capacitance, it is necessary to keep the potential of the semiconductor substrate constant. Therefore, as in the conventional example described above, the semiconductor substrate and the surface electrode are electrically connected to keep the potential of the semiconductor substrate constant.In order to make the potential of the semiconductor substrate uniform, it is necessary to resistance value must be reduced. Furthermore, when a high frequency signal current is induced in the semiconductor substrate through the parasitic capacitance, this induced high frequency signal ffl flow causes crosstalk between elements and circuits. In order to reduce the occurrence of crosstalk, measures are taken to absorb the above-mentioned induced high frequency current near its source. The means for this is the same as the method for the parasitic capacitance described above, and is to electrically connect the semiconductor substrate and the surface electrode, and to maintain the surface electrode at a constant potential. The effect becomes greater as the resistance value between the semiconductor carrier and the surface electrode becomes smaller. According to the conventional semiconductor device described above, the resistance between the semiconductor substrate and the surface electrode can be reduced. That is, when designing a semiconductor device for use in a high frequency band, a method is used to provide as wide an electrical connection area between a semiconductor substrate and a surface electrode as possible within a range that does not adversely affect capacitive coupling between circuits. [Problems to be Solved by Chiriaki] In the above-mentioned conventional technology, the electrical connection between the semiconductor substrate and the surface electrode has a double structure, and the resistance value is lowered by the peripheral low-resistance second region. Therefore, the resistance value is determined by the peripheral length of the second region, which is approximately equal to the peripheral length of the opening. So, for example. Proportionally doubling the area of the aperture would only increase the perimeter by 72 times, and the resistance would increase by almost 0.7 times, or about 30
% reduction. The purpose of the present invention is to: As an application of the prior art, it is an object of the present invention to provide a structure that reduces the resistance value between a semiconductor substrate and a surface electrode without increasing the area of the surface electrode.
上記目的を達成するために、第１領域と第２領域で構成
した電気的接続部を半導体装置の形成上杵される範囲内
で小さくし、電気的接続部のサイズに応じて１つの表面
電極部を複数の領域に分割し、分割した表面電極部の各
々に上記接続部を配置したものである。
また、上記表面電極を外部の電気端子と接続するために
、半導体装置表面上に設ける接続部（以下、パッドと称
する）の直下に、上述の構成を有する構造とすることに
より、本発明の効果を一層高めることができる。
［作用］
本発明の作用を以下の条件を前提として説明する。
（１）第２領域の抵抗値が第１領域の抵抗値よりも十分
小さい。
（２）第２領域の開口周辺長に対する単位長当りの抵抗
値をｒとする。
（３）開口部を矩形として各辺の長さをＷ、Ｌとする。
（４）上記第２領域の最小形成可能寸法をＸとする。
以上の条件に従い、半導体基体と表面電極との電気的接
続部の抵抗値を、従来技術による場合と本発明による場
合とにおいて比較する。
従来技術を用いた場合、電気的接続部の抵抗値Ｒ１は、
Ｒ１＝ ｒ／（２（Ｗ＋Ｌ））
となる。一方、本発明を用いた場合の電気的接続部の抵
抗値Ｒ２は、
Ｒ２＝（ｒ／４Ｘ）／（Ｗ−Ｌ／Ｘ”）となる。Ｒ１と
Ｒ２の比りを取ると、
Ｄ＝Ｒ２／Ｒ１＝（Ｘ（Ｗ＋Ｌ））／ （２Ｗ−Ｌ）と
なる。例えば、Ｗ＝Ｌ＝１００μｍ、Ｘ＝１０μｍとす
るとＤ＝１／１０になり、本発明によって表面電極の面
積を広げることなしに抵抗値を低減することができる。In order to achieve the above object, the electrical connection portion composed of the first region and the second region is made as small as possible within the range of forming the semiconductor device, and one surface electrode is formed according to the size of the electrical connection portion. The electrode section is divided into a plurality of regions, and the connection section is arranged in each of the divided surface electrode sections. Furthermore, the effects of the present invention can be achieved by providing a structure having the above-mentioned configuration directly below a connection portion (hereinafter referred to as a pad) provided on the surface of a semiconductor device in order to connect the surface electrode to an external electrical terminal. can be further enhanced. [Operation] The operation of the present invention will be explained based on the following conditions. (1) The resistance value of the second region is sufficiently smaller than the resistance value of the first region. (2) Let r be the resistance value per unit length with respect to the opening peripheral length of the second region. (3) The opening is a rectangle and the lengths of each side are W and L. (4) Let X be the minimum formable dimension of the second region. Under the above conditions, the resistance value of the electrical connection between the semiconductor substrate and the surface electrode will be compared between the conventional technique and the present invention. When the conventional technology is used, the resistance value R1 of the electrical connection part is R1=r/(2(W+L)). On the other hand, the resistance value R2 of the electrical connection when using the present invention is R2=(r/4X)/(W-L/X"). Taking the ratio of R1 and R2, D= R2/R1=(X(W+L))/(2W-L).For example, if W=L=100 μm and X=10 μm, D=1/10, and the area of the surface electrode can be expanded by the present invention. It is possible to reduce the resistance value without any resistance.
以下、本発明の一実施例を第１図により説明する。
（実施例１）
第１図は、半導体装置の上面図である。第１図（ａ）は
、本発明の一実施例、第１図（ｂ）は、従来例である。
第１図（ａ）の実施例では、表面電極２で覆った領域を
４等分した。その結果、前述の式あるいは第１図から、
抵抗率の低い第２導電領域４の周辺長は従来例と比べて
約２倍となり、半導体基体１と表面電極２間の抵抗値は
約１７２になる。このように、表面電極部を分割し、第
１導電領域３と第２導電領域４で構成した接続部を複数
設けることで半導体基体１と表面電極２間の抵抗値を低
減することができる。
（実施例２）
本発明の他の実施例を第３図に示す。第１図（ａ）との
差異は隣接する第２導電領域４が互いに間隙を有してい
ることである。半導体装置の作成において、第１導電領
域３の間隔が制限される等、第２導電領域４を接触でき
ないの場合に用いる。この場合、第２導電領域４の総局
辺長は、第１図（ａ）に示した実施例と比較して若干短
くなり、わずかに抵抗値が大きくなる。
（実施例３）
本発明のさらに他の実施例を第４図に示す。
第４図は実装基板上に配置した半導体装置の部分上面図
である。半導体装置に形成した回路と実装基板１１との
電気的接続法の代表例は、第４図に示すように半導体装
置上面にパッド１２．１３を設け、導電性ワイヤ１８．
１９を用いて実装基板１１上の基板配線バタン１６．１
７と接続する方法である。
第４図において、パッド１３は配線パタン１５を介して
半導体装置内の回路に接続されているとする。一方、パ
ッド１２は配゛線パタン１４を介して半導体基体１との
接続部に接続されているとする。パッド１２．１３の寸
法はワイヤボンディング装置に依存するが一辺１００μ
ｍ前後が一般的である。
上記の実施例は、半導体基体１との接続部に電気的に接
続されているパッドエ２の直下に、半導体基体１との接
続部を、前記第１もしくは第２の実施例で説明したよう
に分割して設けたものである。本実施例は動作的には、
第１、第２の実施例と同様であり、パッド１２の直下の
有力利用を図り、半導体基体ｌと表面電極およびパッド
１２間の抵抗値を低減したものである。An embodiment of the present invention will be described below with reference to FIG. (Example 1) FIG. 1 is a top view of a semiconductor device. FIG. 1(a) shows an embodiment of the present invention, and FIG. 1(b) shows a conventional example. In the example shown in FIG. 1(a), the area covered with the surface electrode 2 was divided into four equal parts. As a result, from the above formula or Figure 1,
The peripheral length of the second conductive region 4 having low resistivity is approximately twice that of the conventional example, and the resistance value between the semiconductor substrate 1 and the surface electrode 2 is approximately 172. In this manner, the resistance value between the semiconductor substrate 1 and the surface electrode 2 can be reduced by dividing the surface electrode portion and providing a plurality of connection portions composed of the first conductive region 3 and the second conductive region 4. (Example 2) Another example of the present invention is shown in FIG. The difference from FIG. 1(a) is that adjacent second conductive regions 4 have a gap between them. In manufacturing a semiconductor device, it is used when the second conductive regions 4 cannot be brought into contact, such as when the interval between the first conductive regions 3 is restricted. In this case, the total side length of the second conductive region 4 will be slightly shorter than in the embodiment shown in FIG. 1(a), and the resistance value will be slightly larger. (Example 3) Still another example of the present invention is shown in FIG. FIG. 4 is a partial top view of the semiconductor device placed on the mounting board. A typical example of an electrical connection method between a circuit formed in a semiconductor device and the mounting board 11 is as shown in FIG.
19 using the board wiring button 16.1 on the mounting board 11.
This is a method to connect with 7. In FIG. 4, it is assumed that the pad 13 is connected to a circuit within the semiconductor device via a wiring pattern 15. On the other hand, it is assumed that the pad 12 is connected to the connection portion with the semiconductor substrate 1 via the wiring pattern 14. The dimensions of pads 12 and 13 depend on the wire bonding equipment, but each side is 100μ.
Generally, it is around m. In the above embodiment, the connection portion with the semiconductor substrate 1 is placed directly under the pad 2 which is electrically connected to the connection portion with the semiconductor substrate 1, as described in the first or second embodiment. It was set up separately. This embodiment operates as follows:
This is similar to the first and second embodiments, and the area directly under the pad 12 is effectively utilized to reduce the resistance value between the semiconductor substrate l, the surface electrode, and the pad 12.
本発明によれば、半導体基体と表面ｆｆｉ［ｉとの接続
部を細分化することにより、表面電極の単位面積当りの
抵抗値を低減する効果がある。その結果、半導体基体の
電位を一定に近づけることができ、寄生容量を安定化で
きる。また、半導体基体に誘起された高周波電流を、表
面電極において効率良く吸収できる。
さらに１、外部端子と電気的接続のために用いるパッド
の直下に本発明の構造を適用することによって、半導体
基体との電気的接続に関し、半導体装置の有効利用を図
る効果がある。According to the present invention, by subdividing the connection portion between the semiconductor substrate and the surface ffi[i, it is possible to reduce the resistance value per unit area of the surface electrode. As a result, the potential of the semiconductor substrate can be kept close to constant, and the parasitic capacitance can be stabilized. Furthermore, high frequency current induced in the semiconductor substrate can be efficiently absorbed in the surface electrode. Furthermore, 1. By applying the structure of the present invention directly under a pad used for electrical connection with an external terminal, there is an effect that the semiconductor device can be used effectively with respect to electrical connection with a semiconductor substrate.
第１図は本発明の一実施例と従来例を示す半導体装置の
上面図、第２図は従来の半導体基体と表面電極との接続
部を示す半導体装置の断面図、第３図は本発明の他の実
施例を示す半導体装置の上面図、第４図は本発明のさら
に他の実施例を示す実装基板を含む半導体装置の部分上
面図である。
符号の説明
１・・・半導体基体、２・・・表面電極、３・・・第１
導電領域、４・・・第２導電領域、５．６・・・高濃度
Ｊ？５．７・単結晶Ｓｉ、８・・・多結晶Ｓｉ、９．１
０・・・酸化膜、ｌ１実装基板、１２．１３・・・パッ
ド、１４．１５・・配線バタン、１６．１７・・・基板
配線バタン、１８．１９・・・導電性ワイヤ
（Ｌ）
（ｂ）FIG. 1 is a top view of a semiconductor device showing an embodiment of the present invention and a conventional example, FIG. 2 is a sectional view of a semiconductor device showing a connection between a conventional semiconductor substrate and a surface electrode, and FIG. 3 is a top view of a semiconductor device according to the present invention. FIG. 4 is a partial top view of a semiconductor device including a mounting board showing still another embodiment of the present invention. Explanation of symbols 1...Semiconductor substrate, 2...Surface electrode, 3...First
Conductive region, 4...Second conductive region, 5.6...High concentration J? 5.7. Single crystal Si, 8... Polycrystalline Si, 9.1
0... Oxide film, l1 mounting board, 12.13... Pad, 14.15... Wiring button, 16.17... Board wiring button, 18.19... Conductive wire (L) ( b)
Claims (1)
を有する絶縁物と、前記開口部のほぼ直上に設けられた
高抵抗な第１導電領域と、前記絶縁膜上に設けられると
共に前記第１導電領域のほぼ垂直な側壁と接するように
設けられた低抵抗な第２導電領域と、前記第１導電領域
ないし前記第２導電領域の少なくとも一部を覆う金属と
を有し、前記金属と前記半導体基体とが電気的に接続さ
れている半導体装置において、１つの前記金属に対して
、前記第１導電領域と第２導電領域で構成した半導体基
体と半導体装置表面金属との接続部を複数に分け、隣接
させて配置したことを特徴とする半導体装置。 ２、請求項１記載の、半導体基体と半導体装置表面金属
との接続部を、半導体装置と外部端子との接続用に半導
体装置上に設けた電極の直下に設けたことを特徴とする
半導体装置。[Claims] 1. A first conductivity type semiconductor substrate, an insulator having an opening on the surface of the substrate, a high-resistance first conductive region provided almost directly above the opening, and the insulator. a low-resistance second conductive region provided on the film and in contact with a substantially vertical sidewall of the first conductive region; and a metal covering at least a portion of the first conductive region or the second conductive region. and a semiconductor device in which the metal and the semiconductor substrate are electrically connected, the semiconductor substrate comprising the first conductive region and the second conductive region for one of the metals, and the semiconductor device. A semiconductor device characterized in that a connection part with a surface metal is divided into a plurality of parts and arranged adjacent to each other. 2. A semiconductor device according to claim 1, wherein the connection portion between the semiconductor substrate and the surface metal of the semiconductor device is provided directly below an electrode provided on the semiconductor device for connection between the semiconductor device and an external terminal. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19656589A JPH0362565A (en) | 1989-07-31 | 1989-07-31 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19656589A JPH0362565A (en) | 1989-07-31 | 1989-07-31 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0362565A true JPH0362565A (en) | 1991-03-18 |
Family
ID=16359850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19656589A Pending JPH0362565A (en) | 1989-07-31 | 1989-07-31 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0362565A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5311061A (en) * | 1993-05-19 | 1994-05-10 | Motorola Inc. | Alignment key for a semiconductor device having a seal against ionic contamination |
| KR100854578B1 (en) * | 2007-05-02 | 2008-08-26 | 태성이엔씨(주) | Installation method by pre-setting pile composite wall |
-
1989
- 1989-07-31 JP JP19656589A patent/JPH0362565A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5311061A (en) * | 1993-05-19 | 1994-05-10 | Motorola Inc. | Alignment key for a semiconductor device having a seal against ionic contamination |
| KR100854578B1 (en) * | 2007-05-02 | 2008-08-26 | 태성이엔씨(주) | Installation method by pre-setting pile composite wall |
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