JPH0362736A - Series-parallel AD converter - Google Patents

Abstract

PURPOSE:To increase the conversion speed of a serial/parallel A/D converter by providing two sample-and-hold circuits sampling an input signal with a switching signal and repeating the sampling by the circuits alternately. CONSTITUTION:When a high-order changeover switch 3 is thrown to the position of a sample-and-hold circuit 2A, a high-order A/D converter 4 AD-converts an output of the sample-and-hold circuit 2A. When the AD conversion is finished, the high-order changeover switch 3 is thrown to the position of a sample-and- hold circuit 2B, and the high-order A/D converter 4 AD-converts an output of the sample-and-hold circuit 2B. The low-order changeover switch 5 is thrown to the position of a sample-and-hold circuit 2A till the high-order A/D converter 4 finishes the conversion of the output of the sample-and-hold circuit 2A, and as soon as the high-order A/D converter 4 finishes the conversion of the output of the sample-and-hold circuit 2A, the low-order A/D converter 6 starts the conversion. Thus, high speed A/D conversion is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a series/parallel type AD converter that converts an analog signal into a digital signal.

Conventional technology Figure 3 shows the configuration of a conventional serial-parallel AD converter.
The figure shows the timing of each part in the figure.

In the serial-parallel AD converter shown in Figure 3, input signal 1 is
When converting (as shown in Figure 4, first the upper AD
The converter 4 roughly converts the output voltage of the sample and hold circuit 2 into A
After D conversion, the output voltage of the sample hold circuit 2 is finely AD converted using the outputs of the lower AD converters 6 and the upper AD converter 4. Therefore, it is necessary to hold the output voltage of the sample and hold circuit 2 (from the time when the upper AD converter 4 starts conversion until the lower AD converter 6 finishes conversion) constant.

Problems to be Solved by the Invention As can be seen from FIG. 4, the conversion time of the series-parallel AD converter shown in FIG. This invention was made as a result of devising and researching the drawbacks of the above-mentioned serial-parallel type AD converters. Another purpose is to provide an AD converter that is faster than conventional ones.

Means for Solving the Problems The present invention ζ In order to solve the above problems, two sample-and-hold circuits sample an input signal using a switching signal, and one of the outputs of the two sample-and-hold circuits is selected. "Output" 1st-level changeover switch and upper-level A that coarsely AD converts the output of the higher-level changeover switch.
a D converter, a lower selector switch that selects and outputs one of the outputs of the sample and hold circuit, and a lower AD converter that finely AD converts the output of the lower selector switch using the output of the upper AD converter. This is a series/parallel type AD converter.

Effect of the present invention With the above-described configuration, one of the two sample and hold circuits (referred to as A) samples the input signal.
The upper level changeover switch is connected to the sample/halt circuit A, and rough AD conversion is performed by the upper level AD converter. Before this conversion is completed, the lower selector switch is connected to the sample and hold circuit A, and the lower AD converter finely AD converts the output of the sample and hold circuit A using the output of the upper AD converter. On the other hand, at the same time as the conversion by the higher-order AD converter ends, the upper-order changeover switch is connected to another sample-and-hold circuit (referred to as B), and the higher-order AD converter starts AD conversion. The upper AD converter can start converting the next B output without waiting for the lower AD converter to finish converting the A output.

By repeating this alternately, the conversion interval of this series-parallel AD converter is 1. Upper AD converter and lower A
The conversion time is approximately equal to the conversion time of the slower one of the D converters, and high-speed AD conversion can be performed.

Embodiment FIG. 1 is a block diagram of a series-parallel type AD converter in an embodiment of the present invention. Examples will be described below with reference to the drawings.

Input signal 1 is input to two sample and hold circuits 2A,
Sample in 2B alternately. Upper selector switch 31 Selects and outputs one of the two sample and hold circuits' 2B outputs. The upper AD converter 4 roughly performs AD conversion on the output of the upper selector switch 3. Lower selector switch 5LL, two sample hold circuits 2A, 2
B selects and outputs one of the outputs, and the lower AD converter 6 uses the output of the upper AD converter 4 to switch to the lower selector switch 5.
The output is finely AD converted.

FIG. 2 shows the timing of switch switching and data output at this time. S is sample hold circuit 2A,
2B indicates that the input is taken in, and H indicates that the output voltage is held constant. Also, switches A and B should be connected to sample and hold circuits 2A and 2B, respectively.
When the upper selector switch 3 is connected to the side of the two sample and hold circuits, the upper AD converter 4 AD converts the output of the sample and hold circuit 2A. When that is finished, the upper selector switch 3 switches to the sample hold circuit 2B.
The upper AD converter 4 AD converts the output of the sample hold circuit 2B. By the time the upper AD converter 4 finishes converting the output of the sample and hold circuit 2A, the lower changeover switch 5 switches to the sample and hold circuit 2A.
The upper AD converter 4 finishes AD conversion of the outputs of the two sample and hold circuits, and the lower AD converter 4
Converter 6 begins the conversion.

From the above, it is possible to sample and AD convert the next input without waiting for the conversion of the sample and hold circuits 2A, 2B and the upper and lower AD converters 4 (upper and lower AD converters 6) to be completed. A/D conversion is possible.

Effects of the Invention As is clear from the above description, the present invention allows the conversion speed of a series/parallel type AD converter to be greatly increased by adding only a small amount of circuitry. Therefore, the present invention is extremely useful.

[Brief explanation of drawings]

Figure 1 shows the configuration of a series-parallel type AD converter according to an embodiment of the present invention. Figure 2 shows the timing of each part of the series-parallel type A and D converters shown in Figure 1. Figure 3 shows the configuration of a conventional series-parallel type AD converter. Type AD
Converter Configuration @ FIG. 4 is a timing diagram of each part of the series/parallel type AD converter shown in FIG. 3. 1...Input signal, 2A, 2B...Sample hold circuit 3...Upper switch, 4..."
1st place A, D converter 5...lower selector switch,
6...lower AD conversion Atsushishima

Claims (1)

[Claims] Two sample-and-hold circuits that sample input signals using switching signals, an upper-level switch that selects and outputs one of the outputs of the two sample-and-hold circuits, and an upper-level switch that roughly AD converts the output of the upper-level switch. an AD converter, a lower selector switch that selects and outputs one of the outputs of the sample and hold circuit, and a lower AD converter that uses the output of the upper AD converter to finely AD convert the output of the lower selector switch. A series-parallel type AD converter equipped with.