JPS62110322A - Sample-and-hold system - Google Patents

Abstract

PURPOSE:To double the cycle time for one sample-and-hold and to attain analog/ digital conversion with high speed and good stability by providing two sample- and-hold circuits to one A/D converter and using the two sample-and-hold circuits while being switched in time division. CONSTITUTION:An analog signal is inputted to the sample-and-hold circuit, the signal is traced by sampling and the input signal is subjected to holding. In the constitution shown in figure, the two sample-and-hold circuits No.1, No.2 are provided and the two circuits are used while being switched in time division. Since the two sample-and-hold circuits are used in time division, the sufficient sampling time is obtained and the sampling period is quickened as fast as two times of a conventional period.

Description

[Detailed description of the invention] By duplicating the sample and hold circuit,
This invention relates to a sample-and-hold method that can perform high-speed and stable analog-to-digital conversion.

[Conventional technology]

Conventional analog-to-digital conversion devices use one sample-and-hold circuit and one A/D converter; The drawback is that it disappears.

[Problems to be solved by the invention]

An object of the present invention is to use two sample-and-hold circuits in an analog-to-digital converter, so that the two sample-and-hold circuits can be used for time division, and the time per cycle of one sample-and-hold circuit can be substantially reduced. The objective is to provide high-speed and stable analog-to-digital conversion.

[Means for solving problems]

The present invention has two sample and hold circuits for one A/D converter, and by switching and using the two sample and hold circuits in a time division manner, sample and hold circuits are used.
By doubling the cycle time per hold and providing sufficient sampling time, high-speed and stable analog-to-good digital conversion can be performed.

〔Example〕

Figure 3 shows a conventional analog-to-digital conversion configuration diagram;
The figure shows conventional sample and hold timing.

In FIG. 4, an analog signal is input to the sample and hold circuit, which follows the signal by sampling and holds the input signal. When the signal is held in the sample and hold circuit, the A/D converter performs analog-to-digital conversion. This A/D conversion takes "S" time.
After the conversion is completed, the sample and hold circuit starts sampling. This completes one cycle of operation. According to the conventional method, the conversion time "S" is determined by the A/D converter, so if you try to shorten the sampling period (shorten the A/D conversion time "T"), the sampling time will become shorter and the input analog waveform will change. sample·
The hold circuit cannot follow up sufficiently.

FIG. 1 shows a block diagram of analog-to-digital conversion according to the present invention, and FIG. 2 shows sample and hold timing.

The configuration shown in FIG. 1 has two sample-and-hold circuits, and these two circuits are switched and used in a time-division manner.

As can be seen from FIG. 2, since two sample-holds are used in a time-division manner, sufficient sampling time can be obtained, making it possible to increase the sampling period to twice that of the conventional method.

〔Effect of the invention〕

According to the present invention, since the sampling period of the sample-and-hold circuit can be shortened, it is possible to perform A/D conversion of high-frequency analog signals.

[Brief explanation of drawings]

1 and 2 are diagrams for explaining one embodiment of the present invention, and FIGS. 3 and 4 are diagrams for explaining the prior art.

Claims (1)

[Claims] Two sample-and-hold circuits are provided for one analog-to-digital converter, and the analog data held by each sample-and-hold circuit is input to the analog to digital converter alternately in a time-division manner to convert it to digital data. A sample-and-hold method characterized by converting it into a signal.