JPH0363224B2 - - Google Patents

Info

Publication number
JPH0363224B2
JPH0363224B2 JP56197842A JP19784281A JPH0363224B2 JP H0363224 B2 JPH0363224 B2 JP H0363224B2 JP 56197842 A JP56197842 A JP 56197842A JP 19784281 A JP19784281 A JP 19784281A JP H0363224 B2 JPH0363224 B2 JP H0363224B2
Authority
JP
Japan
Prior art keywords
layer
melting point
heat treatment
film
molybdenum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56197842A
Other languages
Japanese (ja)
Other versions
JPS5898963A (en
Inventor
Kohei Higuchi
Hidekazu Okabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56197842A priority Critical patent/JPS5898963A/en
Publication of JPS5898963A publication Critical patent/JPS5898963A/en
Publication of JPH0363224B2 publication Critical patent/JPH0363224B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48Insulating materials thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/62Electrodes ohmically coupled to a semiconductor

Landscapes

  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特に金属とシリコ
ンとのオーミツク接触を有する半導体装置に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device having ohmic contact between metal and silicon.

近年集積回路の高密度化が進むにつれて、
MOS(Metal Oxide Semiconductor)型の集積
回路中のゲート電極配線や電極等の素材として広
く用いられるようになつたものに、不純物添加多
結晶シリコンがある。しかしながら、この不純物
添加多結晶シリコンは、比抵抗が約1mΩ・cmと
高く、集積回路の高密度化が進むにつれて、その
配線抵抗が無視できない事態になつてきた。特に
高密度の応答が困難になる点が問題である。この
ため、最近ではモリブデン等の高融点金属をゲー
ト電極等の配線として用いることにより、抵抗を
下げかつ安定な半導体装置を得ようとする考えが
注目されている。このモリブデン等の高融点金属
は、比抵抗が約10μΩ・cmと、不純物添加多結晶
シリコンに比して、約2桁も小さく、このため配
線抵抗は十分に無視できる程小さくなる。また結
晶粒径も小さく、微細加工性に優れており、高密
度集積回路等の配線材料として多結晶シリコンに
とつて代るべき素材であると考えられる。
As the density of integrated circuits has increased in recent years,
Impurity-doped polycrystalline silicon has become widely used as a material for gate electrode wiring, electrodes, etc. in MOS (Metal Oxide Semiconductor) integrated circuits. However, this impurity-doped polycrystalline silicon has a high specific resistance of about 1 mΩ·cm, and as the density of integrated circuits increases, the wiring resistance has become impossible to ignore. In particular, the problem is that high-density response becomes difficult. Therefore, recently, attention has been paid to the idea of using a high-melting point metal such as molybdenum for interconnections such as gate electrodes to lower resistance and obtain stable semiconductor devices. This high melting point metal such as molybdenum has a specific resistance of about 10 μΩ·cm, which is about two orders of magnitude smaller than that of impurity-doped polycrystalline silicon, and therefore the wiring resistance is sufficiently small to be ignored. Furthermore, it has a small crystal grain size and is excellent in microprocessability, and is considered to be a material that should replace polycrystalline silicon as a wiring material for high-density integrated circuits and the like.

従来の高融点金属たとえばモリブデンゲート電
極として用いたMOS型スタテイツク・メモリ等
の半導体装置に於てはメモリ・セル領域を微小に
するために、ゲート電極の一部が、MOSトラン
ジスタのソースまたはドレイン等のシリコン(以
下Siと記す)上の拡散層領域と直接オーミツク接
触するいわゆるダイレクトコンタクトと称する領
域が存在する。第1図aに示すような回路中の
MOSトランジスタ10がその例である。第1図
aのMOSトランジスタ10の断面図は、第1図
bのようになつており、高融点金属をゲート電極
として用いた場合、通常はソースとなる領域1を
形成後、ゲート電極2を形成して、その後イオン
注入法によりドレインとなる領域3に不純物注入
を行う。その後、ドレイン領域の活性化を行うた
めに、1000℃程度の高温熱処理工程が必要であ
る。この際ソースとなる領域1とゲート電極2と
の接触が高温熱処理に対して、安定で良好なオー
ミツク接触が保存される必要がある。
In semiconductor devices such as MOS-type static memories that use conventional high-melting point metals such as molybdenum as gate electrodes, part of the gate electrode is used as the source or drain of the MOS transistor in order to miniaturize the memory cell area. There is a so-called direct contact region that makes direct ohmic contact with the diffusion layer region on the silicon (hereinafter referred to as Si). In a circuit like the one shown in Figure 1a,
The MOS transistor 10 is an example. The cross-sectional view of the MOS transistor 10 shown in FIG. 1a is as shown in FIG. After that, impurities are implanted into the region 3 that will become the drain by ion implantation. After that, a high temperature heat treatment process of about 1000° C. is required to activate the drain region. At this time, it is necessary that the contact between the region 1 serving as the source and the gate electrode 2 is stable and good ohmic contact is maintained against high-temperature heat treatment.

尚第1図bにおいて、ソース領域はゲート電極
2と接続されており、このゲート電極2は絶縁膜
23で覆われ、ドレイン領域には電極24が設け
られている。また、ゲート電極2下は、絶縁層2
6を介して、チヤンネル領域となるシリコン基板
25となつている。
In FIG. 1b, the source region is connected to the gate electrode 2, which is covered with an insulating film 23, and the drain region is provided with an electrode 24. Further, under the gate electrode 2, an insulating layer 2
6 is connected to a silicon substrate 25 which becomes a channel region.

ところで、一般に高融点金属は、Siとの600℃
程度の比較的低温の熱処理により、いわゆるシリ
サイド反応と呼ばれるSiとの化合物形成反応を生
じ、高融点金属シリサイドが形成される。また、
1000℃程度の高温では、この反応は極めて激し
く、配線として3000Å程度の膜厚の高融点金属を
用いている場合、約2倍の6000Åのシリサイドが
形成され著しい体積変化のために、コンタクト孔
部分と絶縁膜部分とで断切れが生じたり、また大
きな応力のために電極が剥れたり、シリコン基板
に無数の欠陥を作つたりする。その結果、接触抵
抗が極めて大きくなつたり、回路がオープンにな
つたりするため、このようなダイレクトコンタク
トをもつ半導体装置に高融点金属を配線材料とし
て用いる上での大きな障害となつている。
By the way, high melting point metals are generally heated at 600℃ with Si.
The heat treatment at a relatively low temperature causes a so-called silicide reaction to form a compound with Si, and a high melting point metal silicide is formed. Also,
At high temperatures of around 1000°C, this reaction is extremely violent, and when a high melting point metal with a film thickness of around 3000 Å is used as the wiring, silicide with a thickness of 6000 Å, which is approximately twice as thick, is formed, causing a significant volume change that causes the contact hole to become damaged. Discontinuities can occur between the electrode and the insulating film, electrodes can peel off due to large stress, and countless defects can be created in the silicon substrate. As a result, the contact resistance becomes extremely large and the circuit becomes open, which is a major obstacle in using high-melting point metals as wiring materials in semiconductor devices having such direct contacts.

本発明の目的は、特に1000℃程度の高温熱処理
後も安定で良好なオーミツク接触を与える電極構
造を有する半導体装置を提供することにある。
An object of the present invention is to provide a semiconductor device having an electrode structure that provides stable and good ohmic contact even after high-temperature heat treatment, particularly at about 1000°C.

本発明によれば、Siと接触する部分に特に500
Å程度の厚さのシリサイド層を形成し、その上に
高融点金属窒化物層を形成した2層電極構造、又
は必要に応じてその構造上にさらに高融点金属層
を形成した多層電極構造を有する半導体装置が得
られる。
According to the present invention, especially 500
A two-layer electrode structure in which a silicide layer with a thickness of about 100 Å is formed and a refractory metal nitride layer formed thereon, or a multilayer electrode structure in which a refractory metal layer is further formed on the structure as necessary. A semiconductor device having the above structure is obtained.

本発明は、次のような2つの知見に基づいて従
来の問題点を解決している。その1つは、高融点
金属の窒化物は1000℃程度の高温熱処理によつて
もSiと殆んど反応が起きず、シリサイド反応のバ
リヤとなるということである。また他の1つは、
オーミツク接触部分の抵抗を小さくするためには
シリサイド層がSiと高融点金属窒化物層の間にあ
る方が望ましいが、このシリサイド層が厚い場合
には高温熱処理後のストレスのために基板に欠陥
をつくつたり、あるいは剥がれが生じたりするた
めに、結局100Åから1000Å程度の厚さが特に望
ましいということである。ここで、モリブデン
(以下Moと記す)やタングステン(以下Wと記
す)等の高融点金属とSiの反応は、反応生成物が
時間に比例するような反応律速であり、貴金属
(金,銀)やニツケル(Ni)のようにSiとの反応
が拡散律速で律速されているようなものとは、反
応の機構が本質的に異なつている。
The present invention solves the conventional problems based on the following two findings. One of them is that nitrides of high-melting point metals hardly react with Si even when subjected to high-temperature heat treatment at about 1000°C, and act as a barrier to silicide reactions. Another one is
In order to reduce the resistance of the ohmic contact area, it is desirable to have a silicide layer between the Si and the high-melting point metal nitride layer, but if this silicide layer is thick, the stress after high-temperature heat treatment may cause defects in the substrate. A thickness of about 100 Å to 1000 Å is particularly desirable because of the possibility of formation of cracks or peeling. Here, the reaction of high melting point metals such as molybdenum (hereinafter referred to as Mo) and tungsten (hereinafter referred to as W) is rate-limiting in that the reaction products are proportional to time, and noble metals (gold, silver) The reaction mechanism is essentially different from that of nickel (Ni), where the reaction with Si is rate-limited by diffusion.

以下本発明を図面を参照しながら詳細に説明す
る。
The present invention will be explained in detail below with reference to the drawings.

第2図aにおいて、P型のSi基板11上に3000
Åの熱酸化膜12を形成し、次に拡散領域となる
べき部分を部分的に開孔し、その上に400Å程度
の熱酸化膜13を形成する。その後この400Åの
酸化膜13を通してイオン注入法でヒ素イオン
(AS+)を100Kev5×1015cm-2で、Si基板11中に
注入し、1000℃20分の窒素中での熱処理により、
ヒ素イオンを活性化し、n+拡散層14を形成す
る。
In FIG.
A thermal oxide film 12 with a thickness of about 400 Å is formed, then a hole is partially formed in a portion to become a diffusion region, and a thermal oxide film 13 with a thickness of about 400 Å is formed thereon. Thereafter, arsenic ions (AS + ) of 100 Kev5×10 15 cm -2 were injected into the Si substrate 11 through this 400 Å thick oxide film 13 by ion implantation, and heat treated at 1000°C for 20 minutes in nitrogen.
Arsenic ions are activated to form an n + diffusion layer 14.

その後、第2図bに示すように、コンタクト孔
15を開孔し、スパツタ法により第1のモリプデ
ン膜16を約300Å形成し、その後反応性スパツ
タ法により窒化チタン(TiN)膜17を約1000
Å形成し、さらに第2のモリプデン膜18を1500
Å形成する。この第3層目のモリプデン膜18は
配線抵抗を下げるために形成したもので、ここに
TiN膜を2500Å形成してもよい。このようにし
て形成されたn+拡散層14上の電極は、Mo
(1500Å)/TiN(1000Å)/Mo(300Å)となつ
ている。第1層目の300Å厚のMoは、その後の
トランジスタ製造過程により1000℃程度の高温熱
処理を高温処理を受け、最終的にはMo(1500
Å)/TiN(1000Å)/MoSi2(600Å)となる。
これが第2図cであり、n+拡散層14と接触す
る部分はモリブデン・シリサイド(MoSi2)膜1
9となる。
Thereafter, as shown in FIG. 2b, a contact hole 15 is opened, a first molybdenum film 16 of about 300 Å is formed by sputtering, and a titanium nitride (TiN) film 17 of about 1000 Å is formed by reactive sputtering.
A second molybdenum film 18 is formed at a thickness of 1,500 Å.
Å form. This third layer of molybdenum film 18 is formed to lower wiring resistance, and here
A TiN film of 2500 Å may be formed. The electrode on the n + diffusion layer 14 formed in this way is made of Mo
(1500Å)/TiN (1000Å)/Mo (300Å). The first layer of Mo with a thickness of 300 Å undergoes high-temperature heat treatment at about 1000°C during the subsequent transistor manufacturing process, and finally becomes Mo (1500 Å thick).
)/TiN (1000Å)/MoSi 2 (600Å).
This is shown in FIG .
It becomes 9.

第3図は第2図bのような断面をもつ素子を窒
素雰囲気中で20分の熱処理を施した場合の固有接
触抵抗の熱処理温度依存性を示す特性図である。
特性曲線21が本発名の本実施例に基づいた場合
であり、特性曲線22はモリブデンのみの電極の
場合である。モリブデンのみの電極の場合は、
700℃以上の熱処理では接触抵抗が極めて大きく
増加しているのに対し、本実施例の場合は僅かし
か接触抵抗の増加はみられず、すぐれたオーミツ
ク特性を示すことがわかる。
FIG. 3 is a characteristic diagram showing the dependence of the specific contact resistance on the heat treatment temperature when a device having a cross section as shown in FIG. 2b is subjected to heat treatment for 20 minutes in a nitrogen atmosphere.
The characteristic curve 21 is the case based on the present example of the present invention, and the characteristic curve 22 is the case of the electrode made only of molybdenum. For molybdenum-only electrodes,
In contrast to heat treatment at 700° C. or higher, which causes a very large increase in contact resistance, this example shows only a slight increase in contact resistance, indicating excellent ohmic properties.

以上のように、本発明によれば、特に1000℃程
度の高温熱処理後も極めて特性の安定した良好な
Si金属とのオーミツク接触を有する半導体装置を
作ることができる。
As described above, according to the present invention, even after high-temperature heat treatment of approximately 1000°C, the property is extremely stable and good.
Semiconductor devices with ohmic contact with Si metal can be made.

尚、本発明の実施例では、n+拡散層上のMoSi2
層は、熱処理により形成したが、これはあらかじ
めスパツタ法等で、直接MoSi2を形成してもよ
い。
In addition, in the embodiment of the present invention, MoSi 2 on the n + diffusion layer
Although the layer was formed by heat treatment, MoSi 2 may be directly formed in advance by a sputtering method or the like.

また、本発明の実施例においては、高融点金属
シリサイドとしてMoSi2を高融点金属窒化物とし
てTiNを、高融点金属層の高融点金属としてMo
を用いたが、本発明はこれに限定されるものでは
なく、シリサイドや窒化物を形成する高融点金属
又は高融点金属層の高融点金属がW、タンタリウ
ム(Ta)等他の高融点金属である場合にも有効
である。
In addition, in the embodiment of the present invention, MoSi 2 is used as the refractory metal silicide, TiN is used as the refractory metal nitride, and Mo is used as the refractory metal of the refractory metal layer.
However, the present invention is not limited thereto, and the refractory metal forming the silicide or nitride or the refractory metal of the refractory metal layer may be W, tantalium (Ta), or other refractory metal. It is also valid when

【図面の簡単な説明】[Brief explanation of drawings]

第1図aはダイレクトコンタクトを有するメモ
リ・セル中の回路図、第1図bは第1図aのダイ
レクトコンタクトを有するMOSトランジスタの
断面図、第2図a乃至第2図cは本発明の実施例
のオーミツク接触を説明するための断面図、第3
図は第2図の構成の素子から求めた固有接触抵抗
の熱処理温度依存性を示す特性図である。 尚図中、1……ソースとなる領域、2……ゲー
ト電極、3……ドレインとなる領域、10……
MOSトランジスタ、11……P型Si基板、12,
13……熱酸化膜、14……n+拡散層、16,
18……モリブデン膜、17……窒化チタン膜、
19……モリブデン・シリサイド膜、21……窒
化チタン膜等を設けた場合の特性曲線、22……
電極をモリブデンのみで形成した場合の特性曲
線、23……絶縁膜、24……電極、26……絶
縁層、25……シリコン基板。
FIG. 1a is a circuit diagram in a memory cell with direct contact, FIG. 1b is a cross-sectional view of the MOS transistor with direct contact of FIG. 1a, and FIGS. 2a to 2c are Third sectional view for explaining ohmic contact in the embodiment
This figure is a characteristic diagram showing the heat treatment temperature dependence of the specific contact resistance obtained from the element having the structure shown in FIG. In the figure, 1...A region that becomes a source, 2...A gate electrode, 3...A region that becomes a drain, 10...
MOS transistor, 11... P-type Si substrate, 12,
13...thermal oxide film, 14...n + diffusion layer, 16,
18...Molybdenum film, 17...Titanium nitride film,
19...Molybdenum silicide film, 21...Characteristic curve when titanium nitride film, etc. are provided, 22...
Characteristic curve when the electrode is formed only of molybdenum, 23...Insulating film, 24... Electrode, 26... Insulating layer, 25... Silicon substrate.

Claims (1)

【特許請求の範囲】[Claims] 1 金属とシリコンとの間にオーミツク接触を有
する半導体装置に於て、前記シリコンとオーミツ
ク接触をすべき部分に高融点金属シリサイド層を
有し、さらにその高融点金属シリサイド層上に高
融点金属窒化物層を有することを特徴とする半導
体装置。
1. In a semiconductor device having ohmic contact between a metal and silicon, a high melting point metal silicide layer is provided in a portion where ohmic contact is to be made with the silicon, and a high melting point metal nitride layer is further formed on the high melting point metal silicide layer. A semiconductor device characterized by having a physical layer.
JP56197842A 1981-12-09 1981-12-09 Semiconductor device Granted JPS5898963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56197842A JPS5898963A (en) 1981-12-09 1981-12-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56197842A JPS5898963A (en) 1981-12-09 1981-12-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5898963A JPS5898963A (en) 1983-06-13
JPH0363224B2 true JPH0363224B2 (en) 1991-09-30

Family

ID=16381241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56197842A Granted JPS5898963A (en) 1981-12-09 1981-12-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5898963A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58500680A (en) * 1981-05-04 1983-04-28 モトロ−ラ・インコ−ポレ−テツド Semiconductor device with low resistance synthetic metal conductor and method for manufacturing the same
JP2577342B2 (en) * 1985-03-30 1997-01-29 株式会社東芝 Semiconductor device and manufacturing method thereof
JPS62145774A (en) * 1985-12-20 1987-06-29 Agency Of Ind Science & Technol Semiconductor device
JPS62188223A (en) * 1986-01-16 1987-08-17 Sony Corp Manufacture of semiconductor compound
JP2733470B2 (en) * 1993-04-20 1998-03-30 日本保鮮システム株式会社 Circulation duct for installation in the cool box

Also Published As

Publication number Publication date
JPS5898963A (en) 1983-06-13

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