JPH0363225B2 - - Google Patents
Info
- Publication number
- JPH0363225B2 JPH0363225B2 JP56197843A JP19784381A JPH0363225B2 JP H0363225 B2 JPH0363225 B2 JP H0363225B2 JP 56197843 A JP56197843 A JP 56197843A JP 19784381 A JP19784381 A JP 19784381A JP H0363225 B2 JPH0363225 B2 JP H0363225B2
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- point metal
- layer
- film
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/48—Insulating materials thereof
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に係り、特に金属とシリコ
ンとの間にオーミツク接触を有する半導体装置に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device having ohmic contact between metal and silicon.
最近、不純物添加多結晶シリコンのかわりに、
モリブデン等の高融点金属を、ゲート電極等の配
線として用いることにより、抵抗を下げかつ安定
な半導体装置を得ようとする考えが注目されてい
る。このモリブテン（Mo）の高融点金属は、比
抵抗が約10μΩ・cmとなつており、不純物添加多
結晶シリコンの１ｍΩ・cmに比して、約２桁も小
さく、このため配線抵抗は十分に無視できる程小
さくなる。また結晶粒径も小さく、微細加工径に
優れており、高密度集積回路等の配線材料とし
て、多結晶シリコンにとつて代るべき優れた素材
であると考えられる。 Recently, instead of doped polycrystalline silicon,
2. Description of the Related Art The idea of using a high melting point metal such as molybdenum as wiring for gate electrodes and the like to lower resistance and obtain a stable semiconductor device is attracting attention. This high-melting point metal, molybdenum (Mo), has a specific resistance of approximately 10 μΩ・cm, which is approximately two orders of magnitude smaller than that of impurity-doped polycrystalline silicon, which has a resistivity of 1 mΩ・cm. Therefore, the wiring resistance is sufficient. It becomes so small that it can be ignored. Furthermore, it has a small crystal grain size and is excellent in microfabrication diameter, and is considered to be an excellent material to replace polycrystalline silicon as a wiring material for high-density integrated circuits and the like.
従来の高融点金属たとえばモリブデンのゲート
電極として用いたMOS型スタテイク・メモリ等
の半導体装置に於ては、メモリ・セル領域を微小
にするために、ゲート電極の一部が、MOSトラ
ンジスタのソースまたはドレイン等のシリコン
（以下Siと記す）上の拡散層（領域）と直接オー
ミツク接触をするいわゆるダイレクトコンタクト
と称する領域が存在する。第１図ａに示すような
回路中のMOSトランジスタ１０がその例である。
このMOSトランジスタ１０の断面図は第１図６
のようになつており、高融点金属をゲート電機と
して用いた場合、通常はソースとなる領域１を形
成後、ゲート電極２を形成して、その後イオン注
入法により、ドレインとなる領域３に不純物注入
を行う。その後、ドレイン領域の活性化を行うた
めに、1000℃程度の高温熱処理公定が必要であ
る。この際、ソースとなる領域１とゲート電極２
との接触が高温熱処理に対して安定で良好なオー
ミツク接触が保存される必要がある。 In semiconductor devices such as MOS-type static memories that use conventional high-melting point metals such as molybdenum as gate electrodes, part of the gate electrode is used as the source of the MOS transistor or There is a so-called direct contact region that makes direct ohmic contact with a diffusion layer (region) on silicon (hereinafter referred to as Si) such as a drain. An example is a MOS transistor 10 in a circuit as shown in FIG. 1a.
A cross-sectional view of this MOS transistor 10 is shown in FIG.
When a high melting point metal is used as the gate electrode, normally after forming the region 1 which will become the source, the gate electrode 2 is formed, and then impurities are added to the region 3 which will become the drain by ion implantation. Perform the injection. After that, a high temperature heat treatment of about 1000° C. is required to activate the drain region. At this time, the region 1 that becomes the source and the gate electrode 2
It is necessary that the contact with the material be stable against high temperature heat treatment and that good ohmic contact be preserved.
尚第１図ｂにおいて、ソース領域はゲート電極
２と接続されており、このゲート電極は絶縁膜２
３で覆われ、ドレイン領域には電極２４が設けら
れている。また、ゲート電極２下は、絶縁層２６
を介して、チヤンネル領域となるシリコン基板２
５となつている。 In FIG. 1b, the source region is connected to the gate electrode 2, and this gate electrode is connected to the insulating film 2.
3, and an electrode 24 is provided in the drain region. Further, under the gate electrode 2, an insulating layer 26
The silicon substrate 2, which becomes the channel region, is
5.
ところで、一般に高融点金属は、Siと600℃程
度の比較的低温の熱処理により、いわゆるシリサ
イド反応と呼ばれるSiとの化合物形成反応を生
じ、高融点金属シリサイドが形成される。また、
1000℃程度の高温では、この反応は極めて激し
く、配線として3000Å程度の膜厚の高融点金属を
用いている場合、約２倍の6000Åのシリサイドが
形成され著しい体積変化のために、コンタクト孔
部分と、絶縁膜部分とで断切れが生じたり、また
大きな応力のために、電極が剥れたり、シリコン
基板に無数の欠陥を作つたりする。その結果、接
触抵抗が極めて大きくなつたり、回路がオープン
になつたりするため、このようなダイレクトコン
タクトをもつ半導体装置に高融点金属を配線材料
として用いる上での大きな障害となつている。 By the way, in general, when a high melting point metal is heat-treated with Si at a relatively low temperature of about 600° C., a compound formation reaction with Si, called a so-called silicide reaction, occurs, and a high melting point metal silicide is formed. Also,
At high temperatures of around 1000°C, this reaction is extremely violent, and when a high melting point metal with a film thickness of around 3000 Å is used as the wiring, silicide with a thickness of 6000 Å, which is approximately twice as thick, is formed, causing a significant volume change that causes the contact hole to become damaged. Discontinuities may occur between the electrode and the insulating film, and due to the large stress, the electrode may peel off and countless defects may be created in the silicon substrate. As a result, the contact resistance becomes extremely large and the circuit becomes open, which is a major obstacle in using high-melting point metals as wiring materials in semiconductor devices having such direct contacts.
本発明の目的は、特に1000℃程度の高温熱処理
後も安定で良好なSiとのオーミツク接触を与える
電極構造を有する半導体装置を提供するものであ
る。 An object of the present invention is to provide a semiconductor device having an electrode structure that provides stable and good ohmic contact with Si even after high-temperature heat treatment, particularly at about 1000°C.
本発明によれば、Siと接触する部分に特に500
Å程度の厚さのシリサイド層を形成し、その上に
高融点金属炭化物層を形成した２層電極構造、又
は必要に応じその構造上にさらに高融点金属層を
形成した多層電極構造を有する半導体装置が得ら
れる。 According to the present invention, especially 500
A semiconductor having a two-layer electrode structure in which a silicide layer with a thickness of about 1.5 Å is formed and a high-melting point metal carbide layer formed thereon, or a multilayer electrode structure in which a high-melting point metal layer is further formed on the structure as necessary. A device is obtained.
本発明は、次のような２つの知見に基づいて、
従来の問題を解決している。その１つは、高融点
金属の炭化物が1000℃程度の高温熱処理によつて
もSiと反応せず、極めて安定な物質であり、シリ
サイド反応のバリヤとなるということである。ま
た他の１つは、オーミツク接触部分の抵抗を小さ
くするためには、シリサイド層がSiと高融点金属
炭化物層の間にある方が望ましいが、このシリサ
イド層が厚い場合には、高温熱処理のストレスの
ための基板に欠隔をつくつたり、あるいは剥れが
生じたりするために100Åから1000Å程度の厚さ
が特に望ましいということである。 The present invention is based on the following two findings:
Solving traditional problems. One of these is that carbides of high-melting point metals do not react with Si even when subjected to high-temperature heat treatment at about 1000°C, and are extremely stable substances that act as a barrier to silicide reactions. Another reason is that in order to reduce the resistance of the ohmic contact area, it is desirable to have a silicide layer between the Si and the high-melting point metal carbide layer, but if this silicide layer is thick, high-temperature heat treatment may be necessary. A thickness of about 100 Å to 1000 Å is particularly desirable because stress can cause gaps or peeling in the substrate.
以下図面により本発明を詳細に説明する。 The present invention will be explained in detail below with reference to the drawings.
第２図ａ〜ｃは本発明の実施例の製造工程を示
す断面図である。まず、第２図ａにおいて、Ｐ型
のSi基板１１上に3000Åの熱酸化膜１２を形成
し、次に拡散層領域となるべき部分を部分的に開
孔し、その上に400Å程度の熱酸化膜１３を形成
する。その後この400Å酸化膜１３を通してイオ
ン注入法でヒ素イオン（AS +）を100kev、５×
1015cm-2で、Si基板１１中に注入し、1000℃20分
の窒素中での熱処理により、イオンを活性化し、
n+拡散層１４を形成する。 FIGS. 2a to 2c are cross-sectional views showing the manufacturing process of an embodiment of the present invention. First, in FIG. 2a, a thermal oxide film 12 with a thickness of 3000 Å is formed on a P-type Si substrate 11, a hole is partially opened in the part that will become the diffusion layer region, and a thermal oxide film 12 of about 400 Å is applied on top of it. An oxide film 13 is formed. After that, arsenic ions (A S + ) are injected into the 400 Å oxide film 13 at 100 keV and 5× by ion implantation.
The ions were implanted into the Si substrate 11 at 10 15 cm -2 and activated by heat treatment in nitrogen at 1000°C for 20 minutes.
An n + diffusion layer 14 is formed.
その後、第２図ｂに示すように、コンタクト孔
１５を開孔し、スパツタ法により、第１のモリブ
デン膜１６を約300Å形成し、その後アルゴンと
メタンの混合ガス中での反応性スパツタ法によ
り、炭化チタン（TiC）膜１７を約1000Å形成
し、さらにモリブテン膜１８を1500Å形成する。
この第３層目のモリブデン膜１８は、配線抵抗を
下げるために形成したもので、ここにTiC膜を
2500Å程度形成してもよい。このようにして形成
されたn+拡散層１４上の電極は、Mo（1500
Å）／TiC（1000Å）／Mo（300Å）となつてい
る。第１層目の300Å厚のＮはその後のトランジ
スタ製造過程により1000℃程度の高温熱処理を受
け最終的にはMo（1500Å）／TiC（1000Å）／
MoSi2（600Å）となる。これが第２図ｃであり、
n+拡散層１４と接触する部分はモリブデン・シ
リサイド（MoSi2）膜１９となる。第３図は第２
図ｂのような断面を持つ素子を窒素雰囲気中で20
分の熱処理を施した場合の固有接触抵抗の熱処理
温度依存性を示す特性図である。特性曲線２１が
本発明の本実施例に基づいた場合であり、特性曲
線２２はモリブデンのみの電極の場合である。モ
リブデンのみの電極の場合は、700℃以上の熱処
理では接触抵抗が極めて大きく増加しているのに
対し、本実施例の場合は僅かしか接触抵抗の増加
はみられず、すぐれたオーミツク特性を示すこと
がわかる。 Thereafter, as shown in FIG. 2b, a contact hole 15 is opened and a first molybdenum film 16 of about 300 Å is formed by a sputtering method, and then a reactive sputtering method is performed in a mixed gas of argon and methane. , a titanium carbide (TiC) film 17 of about 1000 Å is formed, and a molybdenum film 18 of 1500 Å is further formed.
This third layer of molybdenum film 18 is formed to lower wiring resistance, and a TiC film is used here.
A thickness of about 2500 Å may be formed. The electrode on the n + diffusion layer 14 formed in this way is made of Mo (1500
Å) / TiC (1000 Å) / Mo (300 Å). The first layer of 300 Å thick N is then subjected to high-temperature heat treatment at about 1000°C during the transistor manufacturing process, and finally becomes Mo (1500 Å)/TiC (1000 Å)/
It becomes MoSi 2 (600Å). This is Figure 2c,
A molybdenum silicide (MoSi 2 ) film 19 is in contact with the n + diffusion layer 14 . Figure 3 is the second
A device with a cross section as shown in Figure b is placed in a nitrogen atmosphere for 20 minutes.
FIG. 4 is a characteristic diagram showing the dependence of specific contact resistance on heat treatment temperature when heat treatment is performed for 30 minutes. Characteristic curve 21 is the case based on this embodiment of the invention, and characteristic curve 22 is the case for an electrode made only of molybdenum. In the case of an electrode made only of molybdenum, the contact resistance increases significantly when heat treated at 700°C or higher, whereas in the case of this example, only a slight increase in contact resistance is observed, indicating excellent ohmic characteristics. I understand that.
以上のように、本発明によれば、特に1000℃程
度の高温熱処理後も極めて特性の安定した良好な
Siと金属との間のオーミツク接触を有する半導体
装置を作ることができる。 As described above, according to the present invention, even after high-temperature heat treatment of approximately 1000°C, the property is extremely stable and good.
Semiconductor devices can be made with ohmic contact between Si and metal.
本発明の実施例では、n+拡散層上のMoSi2層
は、熱処理により形成したが、これはあらかじめ
スパツタ法等で直接MoSi2を形成してもよい。 In the examples of the present invention, the MoSi 2 layer on the n + diffusion layer was formed by heat treatment, but the MoSi 2 layer may be directly formed in advance by a sputtering method or the like.
また、本発明の実施例においては、高融点金属
シリサイドとしてMoSi2を、高融点金属炭化物と
してTiCを、高融点金属としてMoを用いたが、
本発明はこれに限定されるものではなく、シリサ
イドや炭化物を形成する高融点金属又は高融点金
属層の高融点金属がタングステンＷ、タンタル
Ta等の高融点金属である場合にも有効である。 In addition, in the examples of the present invention, MoSi 2 was used as the high melting point metal silicide, TiC was used as the high melting point metal carbide, and Mo was used as the high melting point metal.
The present invention is not limited to this, and the high melting point metal forming the silicide or carbide or the high melting point metal of the high melting point metal layer is tungsten W, tantalum.
It is also effective in the case of high melting point metals such as Ta.
第１図ａはダイレクトコンタクトを有するメモ
リ・セル中の回路図、第１図ｂは第１図ａのダイ
レクトコンタクトを有するMOSトランジスタの
断面図、第２図ａ乃至第２図ｃは本発明の実施例
のオーミツク接触を説明するための断面図、第３
図は第２図の構成の素子から求めた固有接触抵抗
の熱処理温度依存性を示す特性図である。
尚図中、１……ソースとなる領域、２……ゲー
ト電極、３……ドレインとなる領域、１０……
NOSトランジスタ、１１……Ｐ型Si基板、１２，
１３……熱酸化膜、１４……n+拡散層、１６，
１８……モリブデン膜、１７……炭化チタン膜、
１９……モリブデン・シリサイド膜、２１……炭
化チタン等を設けた場合の特性曲線、２２……電
極をモリブデンのみで形成した場合の特性曲線、
２３……絶縁膜、２４……電極、２６……絶縁
層、２５……シリコン基板。
FIG. 1a is a circuit diagram in a memory cell with direct contact, FIG. 1b is a cross-sectional view of the MOS transistor with direct contact of FIG. 1a, and FIGS. 2a to 2c are Third sectional view for explaining ohmic contact in the embodiment
This figure is a characteristic diagram showing the heat treatment temperature dependence of the specific contact resistance obtained from the element having the structure shown in FIG. In the figure, 1...A region that becomes a source, 2...A region that becomes a gate electrode, 3...A region that becomes a drain, 10...
NOS transistor, 11... P-type Si substrate, 12,
13...thermal oxide film, 14...n + diffusion layer, 16,
18...Molybdenum film, 17...Titanium carbide film,
19...Molybdenum silicide film, 21...Characteristic curve when titanium carbide etc. is provided, 22...Characteristic curve when the electrode is formed only with molybdenum,
23... Insulating film, 24... Electrode, 26... Insulating layer, 25... Silicon substrate.
Claims (1)
する半導体装置に於て、前記シリコンとオーミツ
ク接触をすべき部分に高融点金属シリサイド層を
有し、さらにその高融点金属シリサイド層上に高
融点金属炭化物層を有することを特徴とする半導
体装置。1. In a semiconductor device having ohmic contact between a metal and silicon, a high melting point metal silicide layer is provided in a portion where ohmic contact is to be made with the silicon, and a high melting point metal carbide is further provided on the high melting point metal silicide layer. A semiconductor device characterized by having a layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56197843A JPS5898968A (en) | 1981-12-09 | 1981-12-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56197843A JPS5898968A (en) | 1981-12-09 | 1981-12-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5898968A JPS5898968A (en) | 1983-06-13 |
| JPH0363225B2 true JPH0363225B2 (en) | 1991-09-30 |
Family
ID=16381257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56197843A Granted JPS5898968A (en) | 1981-12-09 | 1981-12-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5898968A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4920071A (en) * | 1985-03-15 | 1990-04-24 | Fairchild Camera And Instrument Corporation | High temperature interconnect system for an integrated circuit |
| JP2507567B2 (en) * | 1988-11-25 | 1996-06-12 | 三菱電機株式会社 | MOS field effect transistor formed in semiconductor layer on insulator substrate |
| JP3086556B2 (en) * | 1993-02-09 | 2000-09-11 | 株式会社神戸製鋼所 | Heat resistant ohmic electrode on semiconductor diamond layer and method of forming the same |
-
1981
- 1981-12-09 JP JP56197843A patent/JPS5898968A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5898968A (en) | 1983-06-13 |
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