JPH0363851A - Cache memory - Google Patents

Abstract

PURPOSE:To prevent excessive access to a main memory performed by providing an address register which holds an invalidation history bit and a flashing targeted address tag, and a comparator which compares the address register with an address tag in a cache. CONSTITUTION:The comparator 10 compares the address register 9 with a cache tag 4 in access from a processor 2, and delivers a comparison result 101 to an invalidation control circuit 12. The invalidation control circuit 12 monitors rewrite to another processor, and resets an effective bit 5 corresponding to data in which its own data is rewritten when holding the data, and cuts the invalidation history bit 6. Also, the invalidation history hit(IH) 6 is referred when the address tag 4 hits on the access from the processor 2 and also the effective bit 5 is reset, and when no (IH) 6 is reset and also noncoincidence in the comparison result 101 of the comparator 10 is obtained, the effective bit 5 is set and the data in the cache is delivered to the processor. Thereby, excessive access to the main memory is evaded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory, and more particularly to a memory having an invalidating means for controlling consistency with a main memory.

[Conventional technology]

The conventional cache, :L memory only resets the valid bit of the data to be invalidated, whether it is invalidated by the first invalidation means or the second invalidation means. .

[Problem to be solved by the invention]

The conventional cache memory mentioned above may be invalidated even though there is no actual data mismatch with the main memory, and if the data is accessed by the processor, the data itself may be invalidated. is held but the valid bit is reset, resulting in a miss, resulting in an access to the main memory, which has the disadvantage of slowing down the process' sleep.

An object of the present invention is to prevent excessive access to main memory by treating data that is not subject to flushing as valid for access from a processor even if all data is invalidated by a flushing command. The objective is to provide a cache memory that can

[Means to solve the problem]

The configuration of the present invention is such that the first processor monitors the rewriting of the main memory of another processor and, if the rewritten data is held, invalidates the data by resetting the valid bit of this data. and a second invalidation means for invalidating all data in the cache by resetting valid bits of all data in the cache by a flushing instruction from a processor, wherein the first an address register that holds an invalidation history bit indicating that it has been invalidated by the invalidating means and an address tag to be flushed from the process; and a comparator that compares this address register with the address tag in the cache. If the address tag is hit and the valid bit is reset in response to an access from the processor, the invalidation history bit is referenced and if the invalidation history bit is not set, the address tag and the address register are If they do not match, a valid bit is set and the data in the cache is controlled to be passed to the processor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. A processor 2 is connected to an address bus 102 and a data bus 103 via a cache memory 1 of this embodiment. The processor 2 outputs an address 201 and inputs/outputs data 202 to the cache memory 1, and also outputs a flushing instruction 203 and a flushing target address 204. The cache directory 3 is divided into three fields: an address tag 4, a valid bit (V)S, and an invalidation history bit (IH) 6, and data 7 holds cache data. The all data invalidation circuit 8 resets all valid bits 5 of the cache directory 3 in response to a flushing instruction 203 from the processor 2.

Address register 9 holds a flushing target address 204 from processor 2 . Comparator 10 is processor 2
Compares address register 9 and cache tag 4 when accessing from
2, the invalidation control circuit 12 monitors the rewriting to the main memory of other processors, and if it holds the rewritten data, resets the valid bit 5 corresponding to that data and records the invalidation history. Cut bit 6. Also, when the address tag 4 is hit in response to an access from the processor 2 and the valid bit 5 is reset, the invalidation history bit IH is referenced and the invalidation history bit is not set and the comparator 10 is compared. If the result 101 is a mismatch, valid bit 5 is set.

Next, the operation of this circuit will be explained.

Cache directory 3, data 7, Table 1 (a)
Suppose it were like this. At this time, if the main memory is rewritten by another processor and the data is B at that time, the invalidation control circuit 12 resets the valid bit 5 corresponding to data B and sets the invalidation history bit 6. Table 1 (a) Table 2 Table 1 (b) Next, when a flushing command 203 is issued by the processor and the tag address to be flushed at that time is C, the all data invalidation circuit 8 resets all valid bits 5. C is held in the address register 9. If the processor accesses data A in this state, the address tag 4 matches but the valid bit 5 has been reset, so the invalidation history bit 6 is referred to. Since the invalidation history bit 6 is not set at this time, the contents of the address tag 4 and the contents of the address register 9 are then compared by the comparator 10. In this case, the content of the address tag 4 is a and the content of the address register 9 is C, so there is a mismatch, and the invalidation control circuit 12 sets the valid bit 5 corresponding to data A and sends data A to the processor. (Table 3).

Similar processing occurs when data D is accessed from the Table 3 processor.

If the access from the processor is to data B or data C, the former has the invalidation history bit 6 set, and the latter has the same comparison result between the address register 9 and the address tag 4, so there is no mistake. It will be treated as such.

FIG. 2 is a block diagram of a second embodiment of the present invention. The invalidation control circuit 106 is a flushing command from the invalidation control circuit 12, and the main memory is continuously rewritten by other processors. Issued when At this time, the invalidation control circuit 12 outputs the address on the address bus line 102 to the invalidation control circuit 12, and holds it in the address register 9 according to the invalidation control signal 107.

This embodiment has the advantage that unnecessary invalidation can be prevented not only by flushing commands from the processor 2 but also by flushing the cache memory when the main memory of other processors is continuously rewritten.

〔Effect of the invention〕

As explained above, the present invention has an address register that holds an invalidation history bit and an address tag to be flushed, and a comparator that compares this address register with an address tag in the cache. Even if data that has not occurred is invalidated,
This has the effect that it is possible to prevent excessive main memory access from one processor to another and improve processor throughput.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, and the last figure is a block diagram of a second embodiment of the present invention. 1... Cache memory, 2... Processor, 3...
・Cache directory, 4...Address tag, 5
... Valid bit, 6... Invalidation history bit, 7...
・Cache data, 8... All data invalidation circuit, 9
...Address register, 10...Comparator, 12...
- Invalidation control circuit, 101... Comparator output line, 102
... Address bus, 1.03 ... Data bus, 10
4... Valid pit set/reset signal line, 105.
...Invalidation history pit set/lead line, 106...
Disabling control circuit flushing command line, 107... Address register control line, 108... Disabling control circuit address line, 201... Processor address line, 202...
- Processor data line, 203... Flushing command line, 204... Flushing target address tag line, 30
1... Address tag output line, 801... Line data invalidation signal line, 802... Address register control line, 9
01...Address register output line. 1゛ (Patent Attorney Susumu Uchihara

Claims (1)

[Claims] a first invalidating means that monitors rewriting of the main memory of another processor, and invalidates the data by resetting a valid bit of the data if the rewritten data is retained; The second step is to invalidate all data in the cache by resetting the valid bits of all data in the cache using a flushing instruction from the processor.
an address register that holds an invalidation history bit indicating that the cache memory has been invalidated by the first invalidating means and an address tag to be flushed from the process; a comparator that compares an address register with an address tag in the cache, and when the address tag is hit in response to an access from the processor and the valid bit is reset, the invalidation history bit is referenced and the invalidation is performed. If the change history bit is not set, the address tag is compared with the contents of the address register, and if they do not match, a valid bit is set and the data in the cache is controlled to be passed to the processor. cache memory.