JPH0365736A - System developing tool - Google Patents

Abstract

PURPOSE:To surely trace the change of a required event occurring asynchronously with a bus cycle by holding the occurring state of the specified event changing between trace timings till the trace timing by a trace information holding means. CONSTITUTION:In a system developing tool to trace various kinds of information successively as synchronizing with some definite timing following the operation of a microprocessor 1, the trace information holding means 11 to 14 to hold occurring state of the specified event inside the microprocessor 1 changing between the definite trace timings till the trace timing are provided. Thus, even though huge storage capacity is not secured in a trace memory, the change of the required event occurring asynchronously with the bus cycle surely is caught.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to system development tools such as emulators and logic state analyzers, particularly to tracing techniques therein, and is applied, for example, to tracing the number of instructions held in an instruction prefetch queue. It is related to effective technology.

[Prior art]

An emulator used for system debugging or system evaluation in the development of microprocessor application equipment is an emulator used for system debugging or system evaluation of the target microprocessor (hereinafter simply referred to as target microprocessor) included in the evaluation target microprocessor application equipment (hereinafter simply referred to as target system). This enables software debugging while functions are substituted by an emulation microprocessor. When using this emulator to debug a target program (hereinafter simply referred to as a user program) or perform system evaluation, for example, you can set a breakpoint on the user program and the execution state of the user program reaches that breakpoint. If this is detected, the execution of the user program is stopped.

Until the break occurs, various bus information and control information are accumulated in a storage device called a trace memory in real time according to the execution state of the user program by the emulation microprocessor. The trace information thus accumulated is given to a system development device or the like after the break and is analyzed, and the user program is disassembled, thereby debugging and evaluating the user program and the target system.

By the way, tracing in a conventional emulator is, for example, r68000ASE-1 published by Hitachi, Ltd.
1 User’s Manual” (published in December 1985)
As described on pages 57 and 58, this was performed in bus cycle units or operating clock units. For example, when tracing is performed in units of operating clocks, predetermined information is sequentially traced for each cycle of the emulator's internal clock. Further, tracing in units of bus cycles is performed sequentially in synchronization with the negation timing of an address strobe signal or a data strobe signal that defines a bus cycle, for example. The trace mode in units of operating clocks can be used to trace changes in events that occur asynchronously with bus cycles.

[Problem to be solved by the invention]

However, when the trace mode in units of operating clocks is used to trace changes in events that occur asynchronously with bus cycles.

Trace information cannot be effectively retained unless a huge storage capacity is set in the trace memory. Moreover, when disassembling a user program from trace information, the analysis method becomes extremely complicated because the amount of information is extremely large. However, if you use the above-mentioned trace mode in units of bus cycles, it is not possible to trace all the state changes between trace points, and the user program can be reversed by analyzing the trace contents after a break due to the missing information. There was a problem that it could not be assembled.

In particular, as microprocessors become more sophisticated and operate faster, microprocessors with built-in instruction prefetch queues are being provided, and since the instruction prefetch queue is normally operated asynchronously with the bus cycle, the instruction prefetch queue remains in the prefetch queue. It is not possible to disassemble a user program unless the number of instructions to be executed is captured reliably.1 For example, when processing that involves a branch in the instruction flow such as exception processing, interrupt processing, or reset processing occurs, the prefetch is not performed. It is necessary to be able to easily understand the execution status of instructions being executed in correspondence with each individual instruction, or to be able to easily trace which instruction among prefetched instructions has been executed.

An object of the present invention is to provide a system development tool that can reliably track changes in required events that occur asynchronously with bus cycles without having to secure a huge storage capacity in a trace memory. It is in.

Another object of the present invention is to provide a system development tool capable of tracing desired information so as to provide reliability and ease in disassembling user programs, as well as system depacking and software depacking. There is a particular thing.

Still another object of the present invention is to provide a system development tool that can easily handle disassembly of an operating program of a microprocessor having an instruction prefetch queue.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

(Means for Solving Problem 111) A brief overview of typical inventions disclosed in this application is as follows.

In other words, in a system development tool that traces various information in synchronization with a certain timing according to the operation of a microprocessor, it is possible to trace the occurrence state of a specific event inside the microprocessor that changes between the certain trace timings. A trace information holding means is provided to hold the trace information up to the timing.

At this time, if the information to be traced is not directly output to the outside of the microprocessor, the occurrence state of internal events of the microprocessor that occur asynchronously with the trace timing is reproduced based on the microprocessor's operating state indication signal. Establish a means of tracking events. For example, the number of instructions held in an instruction prefetch queue included in a microprocessor is obtained.

At this time, the trace information holding means does not need to hold all of the information acquired by the event tracking means, and it may be sufficient to selectively hold the information. For example, when the event tracking means acquires the number of instructions held by the instruction prefetch queue, the trace information holding means stores the number of remaining instructions immediately before the first operation code is taken out from the instruction prefetch queue, and the number of instructions remaining immediately before the queue clearing occurs. It is sufficient to maintain the minimum number of remaining instructions in .

In addition, in order to make it possible to reuse the conventional disassembly method and to prevent the amount of trace information from becoming excessive,
It is preferable to set the trace timing for each bus cycle that the microprocessor starts.

[For production]

According to the above means, the trace information holding means:
By retaining the occurrence state of a specific event that changes between trace timings until the trace timing, the occurrence state of a specific event that changes between trace timings can be maintained until the trace timing. Acts to capture the changing occurrence state of specific events, thereby ensuring that changes in required events that occur asynchronously with bus cycles can be captured without requiring a huge amount of storage capacity in the trace memory. to a distant relative.

This ensures reliability and ease in disassembling the user program.

When the number of remaining instructions immediately before the first operation code held in the trace information holding means is traced, the number of remaining instructions from the first operation code traced together with the number of instructions to the second operation code following the first operation code is traced. The execution status of operation codes after 2 is as follows:
It becomes distinguishable from others and can be grasped. Furthermore, by tracing the number of remaining instructions immediately before the queue clearing occurs, it becomes possible to grasp instructions that have been discarded due to the occurrence of processing that involves a branch, such as exception processing or interrupt processing.

This makes it possible to efficiently and easily deal with disassembly of an operating program of a microprocessor having an instruction prefetch queue with less trace information.

〔Example〕

FIG. 1 shows details of a trace circuit portion in an emulator that is an embodiment of the present invention. In the figure, reference numeral 1 denotes a microprocessor for controlling the target system by substituting the functions of a target microprocessor (not shown), and is constituted by an evaluation chip compatible with, for example, an 8086 type microprocessor. The microprocessor 1 is configured to exchange data, address signals, and various control signals with the outside via an emulation bus 2. In FIG. 1, the emulation bus 2 includes a trace timing generation circuit 3, which is typically shown, and a trace memory 4, such as a RAM (random access memory).
In addition, a break control circuit 1, a proxy memory circuit, a host interface circuit, a system program memory, etc., which are not particularly shown, are also connected. The trace timing generation circuit 3 stores the emulation bus 2 in the trace memory 4 at a constant timing for each bus cycle according to the negation timing of a bus strobe signal such as an address strobe signal As (or a data strobe signal, etc.) that defines a bus cycle. Performs timing control for writing information, etc. The break control circuit includes:
It monitors whether an arbitrarily set break condition is met, and when the condition is met, a break signal is generated to stop the emulation operation. The proxy memory circuit is used to compensate for insufficient storage capacity in the user memory space of the target system, or as a storage area for user programs during software debugging. The host interface is interfaced with a system development device, etc., and is used for downloading user programs, controlling emulation operations, transferring trace information, and the like. The system program controls the internal control of the emulator when the user program is not being executed.
The operating program to be executed is stored. still,
When the break signal is asserted, the program space of the microprocessor 1 is switched from the user program space to the system program space. Further, the emulation bus 2 has an interface unit that can be connected to a target processor mounting area of a target system (not shown). By coupling this interface section to the target system, the microprocessor 1 performs proxy control of the target system.

When using this emulator to debug a user program or evaluate a target system (not shown), for example, set a predetermined memory address on the user program as a breakpoint in a break control circuit (not shown), and then execute the user program. Execution of the user program is halted when it is detected that the state has reached its breakpoint. Until the break occurs, the microprocessor 1
Various bus information and control information are accumulated in the trace memory 4 in real time according to the execution status of the user program. The trace information thus accumulated is given to a system development device or the like after the break and is analyzed, and the user program is disassembled to be used for debugging and evaluation of the user program and the target system.

The explanation up to this point is not particularly different from conventional emulators. Hereinafter, a description will be given of the point that it is possible to trace even the occurrence state of a specific event inside the microprocessor that changes between the trace timings of each bus cycle.

The microprocessor 1 may include, but is not particularly limited to, 6
It has a built-in instruction prefetch queue 10 that stores byte instructions in a first-in, first-out format, so that instructions can be pre-fetched from the outside in units of up to 2 bytes at a time. The instruction prefetch operation is performed as appropriate when the data bus is empty or when there are no more instructions in the instruction prefetch queue 10. The number of valid instructions prefetched into the instruction prefetch queue 10 is changed asynchronously with bus cycles in accordance with instruction sequence control. Therefore, this changing state does not necessarily appear on the emulation bus 2.

Therefore, the emulator of this embodiment is provided with an in-queue byte number tracking circuit 11 for externally reproducing the internal operating state of the instruction prefetch queue 3.0 based on the operating state instruction signal of the microprocessor l. Furthermore, in order to maintain the occurrence state of a specific event in the instruction prefetch queue IO until the trace timing by using the output of the number of bytes in the queue tracking circuit 11,
First operation byte number holding circuit 12, queue clearing byte number holding circuit 13, and queue byte number correction circuit 111
4 is provided. Incidentally, all of these circuits 11 to 14 are connected to the operation reference clock signal CL of the microprocessor 10.
Operates in synchronization with K.

The operating state instruction signals of the microprocessor 1 supplied to the number of bytes in queue tracking circuit 11 are not particularly limited, but include the bus high enable signal BHE, the least significant bit AO of the address signal, and the queue status signal Q of 12 bits.
SO, QSI, and 3-bit access type status signals SO to S2. The bus high enable signal BHE and the least significant bit AO of the address signal are:
It is regarded as a signal that instructs the bus access width by the microprocessor 1 to the outside, and as shown in FIG. 3, for example, the lower byte (8 bits) is
Access, upper byte access, word (16 bits)
Access distinction is indicated. The queue status signals QSO and QSI are signals for externally indicating the operating state of the instruction prefetch queue 10. For example, as shown in FIG. The first operation code is retrieved in bytes), the queue clear means that the instructions remaining in the instruction prefetch queue 10 have been invalidated, and the second and subsequent operation codes are retrieved from the instruction prefetch queue 10 in bytes) is shown. The access type status signal 5o-82 is regarded as a signal for indicating to the outside whether the bus cycle is an instruction fetch cycle or a data read/write cycle according to the combination of levels thereof. The in-queue byte number tracking circuit 11 that receives these status indication signals is configured with a 3-bit counter in response to the fact that the storage capacity of the instruction prefetch queue 10 is 6 bytes. This in-queue byte count tracking circuit 11
The tracking process is performed as follows. When a reset or queue clear is instructed, the count value is initialized. When an instruction briftetch cycle is instructed by the access type status signal 5O-S2, the count is incremented by 1 in the case of byte access, and by 2 in the case of word access. Furthermore, when an instruction is given to take out an operation code from the instruction prefetch queue 10, the count is counted down by l.

Therefore, the number of instruction bytes remaining in the instruction prefetch queue 10 is output to the in-queue byte number tracking circuit 11 in real time as a 3-bit count value QCO-QC2.

The number of bytes in the queue correction circuit 14 aligns the trace reference point for the number of remaining bytes of the instruction prefetch queue 10 with the immediately preceding trace point even when the instruction fetch timing from the instruction prefetch queue 10 and the instruction prefetch timing overlap. For example, when an instruction briefetch cycle is instructed by the access type status signal 5o-82, the count data QCO-QC2 of the number of bytes in the queue is set to 1. It is captured in synchronization with the first state of the machine cycle and output as correction data QCCO-QCC2. Incidentally, this operation may always be performed in the first state of one machine cycle, regardless of the access type status signal 5o-82.

When the first operation byte number holding circuit 12 is instructed to retrieve the first operation code by the queue status signals QSO, QSI, the first operation byte number holding circuit 12 stores the count data QCO-QC2 of the number of bytes in the queue or the number of bytes in the queue correction circuit 14. output data QCCO-QCC2 is selectively taken in, and the taken values are outputted to the trace memory 4 as data QISTO-QIST2. Which one is selected is determined by the level of the access type status signal 5o-82, and when an instruction prefetch cycle is designated by this, the correction data QCCO-Q
CC2 is selected, otherwise count data QC
O-QC2 is selected. In addition, the correction data QCCO-Q
If CC2 is selected, the change in the number of instructions due to the brief fetch operation at that time will not be traced.

This does not pose any problem in the disassembling method described later.

The queue clearing byte number holding circuit 13 stores the count data QCO-QC2 of the number of bytes in the queue or the number of bytes in the queue correction circuit 14 when clear processing for the instruction queue 10 is instructed by the queue status signals QSO and QSI. Selectively capture the output data QCCO-QCC2 and set the captured values to data QCLRO to QCLR.
2 to the trace memory 4. Which one is selected is determined by the level of the access type status signal 5o-82, and when an instruction pre-fetch cycle is designated by this, the correction data QCCO-82 is determined.
QCC2 is selected, otherwise the count data Q
CO to QC2 are selected.

Note that in the output data QISTO-QIST2 of the first operation byte number holding circuit 12 and the output data QCLRO-QCLR2 of the queue clearing byte number holding circuit 13, values 0 to 6 are valid, and 7 is invalid. .

FIG. 2 shows an example of a trace operation regarding the number of remaining instruction bytes in the instruction prefetch queue 10. Second
The figure shows two brief fetch cycles (PF
Clear the queue (CLR) before and after Tl, PFT, )
and IS to retrieve the first operation code twice.
The case is shown in which the following trace points (TP,, Tp,) are performed and each trace point (TP,, Tp,) is synchronized to the end of a bus cycle.

According to FIG. 2, when a queue clear (CLR) occurs, the queue clear byte number holding circuit 3 holds the immediately previous queue byte number data QCO to QC2 (3 bytes) and indicates this value. Data QCLRO~QCLIR2
is stored in the trace memory 4 at a trace point (TP). Note that the data QCLRO to QCLR2 are set to an invalid value of 7 at the end of the bus cycle. Further, in response to a queue clear (CLR) instruction, the count value of the in-queue byte number tracking circuit 11 is initialized to O.

In Edward's briefetch bus cycle (PFT□), the number of bytes in the queue tracking circuit 1 responds to the operation instruction.
1 is sequentially counted up in states Tl and T2, and the held value is set to 2.

When the first operation code extraction l5T1) is instructed, the count value 2 of the immediately preceding byte number tracking circuit 11 in the queue is held in the first operation byte number holding circuit 12. . At the same time, the in-queue byte count tracking circuit 11 is counted down by 1, and its held value is set to 1.

The next one word prefetch bus cycle (PFT,
), then IST to extract the first operation code.
, ) are also instructed, so the number of bytes in the queue tracking circuit 11
The value of is left at the count value 2 in the T3 state.

In reality, there is a possibility that the count up due to the second byte brifetch and the countdown due to the extraction of the first operation code overlap, and the output count value of the in-queue byte number tracking circuit 11 may be disturbed on the way. At this time, the in-queue byte number correction circuit 14 performs the corresponding brifetch bus cycle (PF
In state T1 of T, ), the immediately preceding data QCO-QC
The value indicated by 2 is maintained. therefore,
During the first operation, the byte number holding circuit 12 extracts the first operation code.15T2) In response to the instruction, the byte number correction circuit 14 outputs data QCCO-Q.
The value 1 indicated by CC2 is taken in. The value thus taken in is stored in the trace memory 4 at the primary trace point (TP2). When this brief fetch bus cycle (PFT2) is completed, data QISTO-QI
ST2 is changed to an invalid value of 7.

Next, a method for analyzing the information traced in this manner will be described.

First, the point where the first operation code is extracted is found from the value of data QISTO-QIST2. That is, a portion whose value is a valid value of O to 6 is found. And that data QISTO-QIST
It can be seen that the number of instructions indicated by the value 2 was fetched in the previous brieffetch cycle. The same applies when brief fetch cycles overlap when the first operation code is fetched. This is because in such a case, the values QCCO to QCC2 output from the queued byte number correction circuit 14 are taken into the first operation byte number holding circuit 12 and traced. The type of instruction executed before the point thus obtained can be known by disassembling the instructions while referring to other trace information before the point.

Furthermore, for instructions to be executed after that point, the number of bytes of the entire instruction can be grasped by verifying the contents of the first operation code that was brifetched by referring to the trace results, and further referring to other trace information. However, by disassembling the first operation code, the type of instruction associated with the first operation code can be determined.

However, during the above analysis, queue clearing (QCLRO-QC
When LR2=0 to 6) is detected, the instructions corresponding to the number of instruction bits indicated by the value are processed as if they were not executed.

According to the above embodiment, the following effects can be obtained.

(1) The operating state of the instruction prefetch queue 10 built into the microprocessor l is reproduced by the in-queue byte number tracking circuit 11, the first operation byte number holding circuit 12, the queue clearing byte number holding circuit 13, and the queue By the internal byte number correction circuit 14, the instruction prefetch queue 10
Since the state of occurrence of a specific event in , that is, the state of occurrence of first operation code retrieval and queue clearing, is retained until the trace timing, there is no need to set a trace timing that includes all change timings of that specific event. It is possible to reliably capture the occurrence state of a specific event that changes between predetermined trace timings, such as the end of a bus cycle.

(2) Due to the above-mentioned effects, it is possible to reliably capture required operational changes or operational states of the prefetch queue 10 that occur asynchronously with the bus cycle, without having to secure a huge storage capacity in the trace memory 4. I can do it.

(3) With the above-mentioned effect (2), it is possible to reliably and easily disassemble a user program.

(4) By tracing the number of remaining instructions immediately before the fetching of the pre-fetched first operation code and the number of remaining instructions immediately before the queue clearing occurs, disassembly can be reliably performed with less trace information. That is, when the number of remaining instructions immediately before the first operation code is taken out is traced, the execution of the second and subsequent operation codes following the first operation code is traced along with the number of instructions. The state can also be distinguished from others and can be grasped. In addition, by tracing the number of remaining instructions immediately before the queue clearing occurs, it becomes possible to understand instructions that were discarded due to the occurrence of processing that involves branching, such as exception processing or interrupt processing. (5) Correcting the number of bytes in the queue By providing the circuit 14, even if instruction fetching from the instruction prefetch queue 10 and instruction prefetching overlap, the trace reference point for the number of remaining bytes of the instruction prefetch queue 1o can be aligned with the immediately preceding trace point. In this respect as well, disassembly can be facilitated.

(6) As a result of the above-mentioned effects, the instruction prefetch queue 10 can be built-in by simply providing circuits 11 to 14 in the hardware of a conventional emulator, and even if a bus cycle unit tracing method is adopted as in the conventional emulator. It is possible to easily provide an emulator that is compatible with such high-performance microprocessors.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, a case has been described in which the required internal operating state in the instruction prefetch queue is traced, but the present invention is not limited thereto, and the present invention is not limited to this, and the present invention is applicable to microprocessors that cannot be directly traced via an emulation bus or the like. It can also be widely applied to tracing various internal states of. Therefore, the method of tracking the state can be changed as appropriate depending on the required internal event. Further, the function of a circuit such as the in-queue byte number correction circuit can be changed depending on the position of a trace point. Also,
The number of remaining instruction bytes may be traced each time an operation code is retrieved. However, in this case, the amount of trace information increases compared to the above embodiment.

In the above explanation, we have mainly explained the case where the invention made by the present invention is applied to an emulator, which is the field of application that is the background of the present invention, but the present invention is not limited to this, and the present invention is not limited to this, and the present invention is not limited to this, and the present invention is not limited to this, and the present invention is not limited to this. It can be widely applied to

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, since a trace information holding means is provided that holds the occurrence state of a specific event inside the microprocessor that changes between certain trace timings until the trace timing, it is possible to set a trace timing that includes all the change timings of the specific event. Even if there is no trace, it is possible to capture the occurrence state of a specific event that changes between predetermined trace timings. This has the effect that changes in required events that occur asynchronously with bus cycles can be reliably traced without having to secure a huge storage capacity in the trace memory. Therefore, reliability and ease of disassembling the user program can be achieved.

Also, based on the microprocessor's operating state instruction signal, it reproduces the occurrence state of internal events of the microprocessor that occur asynchronously with the trace timing, for example, changes in the number of instructions held in the instruction prefetch queue included in the microprocessor. By providing the event tracking means, it is possible to easily deal with cases where the information to be traced is not directly output to the outside of the microprocessor.

When the number of instructions held by the instruction prefetch queue is acquired by the event tracking means, the number of instructions held by the prefetch queue is
To surely perform disassembly with a small amount of trace information by causing the trace information holding means to hold the number of remaining instructions immediately before fetching the operation code and the number of remaining instructions immediately before the occurrence of queue clearing and tracing these information. I can do it.

As a result of the above-mentioned effects, instruction prefetching can be performed simply by providing a trace information holding means and an event tracking means in the hardware of conventional system development tools such as emulators, and even if the traditional bus cycle-based tracing method is adopted. This has the effect that it is possible to easily provide a system development tool that can be used with a high-performance microprocessor that has a built-in queue or the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a trace circuit portion in an emulator that is an embodiment of the present invention. Figure 2 is a timing chart showing an example of a trace operation related to the number of remaining instruction bytes in the instruction prefetch queue. Figure 3 is an explanatory diagram of signal definitions for externally instructing the bus access width by the microprocessor. Figure 4 is an instruction prefetch queue. FIG. 4 is an explanatory diagram of status signal definitions for externally indicating the operating state of the device. 1...Microprocessor, 2...Emulation bus, 3...Trace timing generation circuit, 4...
・Trace memory, IO...Instruction prefetch queue 11...Number of bytes in queue tracking circuit, 12...First
Byte number holding circuit during operation, 13... Byte number holding circuit when queue clearing, 14... Byte number correction circuit in queue, BHE... Bus high enable signal AO...
Address signal least significant bit, QSO-QSI...queue status signal, 5o-82...access type status signal, AS...address strobe signal, C
LK: Operation reference clock signal.

Claims (1)

[Claims] 1. In a system development tool that traces various information in synchronization with a certain timing according to the operation of a microprocessor, the identification of the inside of the microprocessor that changes between the certain trace timings. A system development tool characterized by having a trace information holding means for holding the occurrence state of an event until the trace timing. 2. An event tracking means is provided for reproducing the occurrence state of an internal event of the microprocessor that occurs asynchronously with the certain trace timing based on an operating state instruction signal of the microprocessor, and the trace information holding means is 2. The system development tool according to claim 1, wherein information acquired by the event tracking means is selectively held. 3. The event tracking means acquires the number of instructions held by an instruction prefetch queue included in the microprocessor, and the trace information holding means acquires the number of instructions remaining immediately before the first operation code is extracted from the instruction prefetch queue. 3. The system development tool according to claim 2, wherein the number of remaining instructions immediately before the queue clearing occurs is held. 4. The system development tool according to claim 1, wherein the trace timing is performed in synchronization with each bus cycle activated by the microprocessor.