JPS62197831A - Data processor - Google Patents

Abstract

PURPOSE:To perform the emulation with an action similar to an actual application state by adding a means which calculates the difference between the address of an instruction under execution and a prefetching address and outputting outside the offset value of said arithmetic means together with the control signal that invalidates the instruction prefetched by an instruction register. CONSTITUTION:The contents of a program counter PC set in an execution unit 6 are supplied directly to a memory access control circuit 7. Then an instruction stored in an FIFO 3 is supplied to a microaddress generating circuit 4 in accordance with the contents supplied to the circuit 7. At the same time, a part of the microinstruction read out of a micro-ROM 1 is supplied to the circuit 7. Based on this partial microinstruction, such a fact that the jump instructions, etc., are not executed in the order of prefetched instructions is detected. In such a case, the circuit 7 outputs the FIFO reset signal F-RES to the FIFO 3 to invalidate all instructions so far prefetched by the FIFO 3.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing technique and a technique that is particularly effective when applied to a method of fetching instructions constituting a program. This invention relates to an effective technique that utilizes a microcomputer that can be loaded with some instructions in advance.

° [Conventional technology] Microcomputers that have been proposed so far include:

Some devices have a FIFO (first-in, first-out) type instruction register that stores in advance several instructions that will follow in addition to the instruction being executed. In this way, by loading the next instruction into the FIFO type instruction register in advance, it is possible to speed up program execution.

By the way, when a user develops a new microcomputer system or its software, debugging is often performed by emulation.

In such emulation, execution of a program is interrupted when a certain instruction in the program is executed, or data on the bus is traced to memory from a certain point. And by parsing the contents of this traced memory.

By clarifying the cause of program runaway, it becomes easier to debug programs and systems.

Therefore, during emulation, data buses and address buses are monitored to detect break points and trace points.

[Problems to be solved by the invention] As mentioned above, an FI that fetches multiple instructions in advance
In a microcomputer having an FO register, when emulation is performed, the instructions and addresses that actually appear on the bus are different from the instructions being executed. Therefore, it is not possible to interrupt program execution at the correct breakpoint or to start tracing from a desired point.

Therefore, in addition to the normal mode in which instructions are prefetched, there is also a mode in which instructions are fetched one by one without prefetching instructions, and this mode is switched using a control register.

A microcomputer has also been proposed that is capable of suspending program execution or starting tracing at a desired point during emulation (PRENTI
CE-HALL, INC.

Englswood C11ffs rMc6802
0 32-Bit Microprocessor
User's Manual, 7-2, 3J).

However, emulation using such a mode switching method has the disadvantage that the system operation during emulation does not match the actual system operation when a user program is run.

An object of the present invention is to enable a microcomputer having an instruction register capable of loading a plurality of instructions in advance to perform emulation with operations similar to those in actual use.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a microcomputer having an instruction register capable of loading multiple instructions in advance is provided with means for calculating the difference (hereinafter referred to as offset) between the address of the currently executing instruction and the prefetch address. A control signal for invalidating the instruction prefetched into the instruction register is outputted together with the offset value to the outside.

[Operation] According to the above-mentioned means, if a FIFO memory (or register) similar to the internal instruction register is connected to the external data bus of the microcomputer and the signals on the bus are taken in, execution starts from the offset value. In addition to being able to know the instructions inside, the contents of the FIFO memory for tracing can always be made to match the contents of the instruction register inside the microcomputer using a control signal to invalidate prefetched instructions. , it is possible to achieve the above-mentioned purpose of making it possible to perform emulation with operations similar to those in actual use.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a microcomputer (including a microprocessor and a single-chip microcomputer).

Although not particularly limited, each circuit block surrounded by a chain line A in the figure is formed on one semiconductor chip such as a single crystal silicon substrate.

The microcomputer of this embodiment includes a microprogram control control section. That is, in an LSI chip A on which a microcomputer is formed, a micro ROM (read only memory) 1 in which a micro program is stored is provided. Micro R
OM1 is accessed by the microaddress decoder 5 and sequentially outputs microinstructions constituting a microprogram.

The microaddress generation circuit 4 generates an address to be supplied to the microaddress decoder 5 based on the operation code of the macroinstruction fetched into the instruction register 3. Micro address decoder 5 decodes this. In response, the first instruction of the microinstruction group including the series of next addresses for executing the macroinstruction is read from the microROM 2. By decoding this microinstruction with the control decoder 2, various temporary registers REG, ~REGn, read data buffer DBR, write data buffer D
BW, arithmetic logic unit ALU and program counter P
A control signal is generated for the execution unit 6, such as C.

The second and subsequent microinstructions in a series of microinstructions corresponding to a macroinstruction are executed by, for example, supplying the code of the netast address field of the microinstruction read immediately before to the microaddress decoder 5. . That is, the second and subsequent microinstructions are read based on the netast address in the previous microinstruction and the address from the microaddress generation circuit 4. In this way, the execution unit 6 is controlled by control signals formed by reading a series of microinstructions, and macroinstructions such as the addition instruction ADD are executed.

In this embodiment, a memory access control circuit 7 is provided which has a function of reading and writing data from an external memory, an internal register, etc. in byte units, word units, or long word units as necessary, although this is not particularly limited. It is being

Further, the instruction register 3 may be FI, although it is not particularly limited.
Macro instructions stored in the external memory are read in byte units by the memory access control circuit 7 accessing the address bus 8, and are supplied to the FIFO (3) via the data bus 9. be done.

In this way, a plurality of operation codes and operands are loaded into the FIFO (3) in advance.

The memory access control circuit 7 is directly supplied with the contents of the program counter PC in the execution unit 6, and the instructions in the FIFO (3) are supplied to the microaddress generation circuit 4 in accordance with the contents.

In this embodiment, a prefetch pointer PPP is provided in the execution unit 6 to hold an address for prefetching. The contents of the prefetch pointer PPP are directly supplied to the memory access control circuit 7, and the prefetch address is output onto the external address bus 8 at an appropriate timing, thereby prefetching the instruction.

The memory access control circuit 7 also includes a micro ROM.
A part of the microinstruction read from I (or a signal decoded from it) is supplied.

Based on this, cases such as jump instructions that are not executed in the order of prefetched instructions are detected. When such a case is encountered, the memory access control circuit 7
For (3), output the FIFO reset signal F-RES. by this.

All instructions previously prefetched into FIFO (3) are invalidated.

In this embodiment, the FIFO reset signal F-RES
can be output to the outside.

Furthermore, in this embodiment, the program counter P
A subtraction circuit 11 is provided to calculate the difference (offset) between the address in C and the address in prefetch pointer PFP, and the offset ○FST obtained here can be output to the outside.

Note that the output terminals of the FIFO reset signal F-RES and offset 0FST can be shared with other pins. In that case, appropriate mode terminals may be provided so that these signals are output to the outside only during emulation.

In the microcomputer of the above embodiment, for example, as shown in FIG.
FIFO memories 21 and 22 that capture the above signals are connected to each bus. Then, it is output from the microcomputer CPU. A selection circuit 23 is provided for forming a signal indicating which one of the addresses and instruction codes in the FIFO memo 'J21+22 including the offset value OF S T 7!11 is currently being executed. Further, the selection circuit 23 receives the FIFO reset signal F-RES output from the microcomputer CPU, and selects the FIFO memory 21 from the FIFO memory 21.
A signal is generated to invalidate the address and instruction stored in the microcomputer 22 in correspondence with the instruction register 3 inside the microcomputer.

This makes it possible to always match the prefetch data in the FIFO memory 21, 22 with the contents of the instruction register 3 in the microcomputer during emulation. However, since it is possible to know which instruction is currently being executed from among the prefetched instructions, it is possible to interrupt program execution at a desired point based on this information.
A trace can be started.

As explained above, in the above embodiment, a means is provided for calculating the offset between the address of the currently executed instruction and the prefetch address, and together with this offset value, a FIFO is provided that invalidates the prefetched instruction in the instruction register. Since the reset signal is output to the outside, if a FIFO memory (or register) similar to the internal instruction register is connected to the external data bus of the microcomputer and the signal on the bus is captured, the above offset value can be obtained. The instruction being executed can be known from the FIF○ reset signal, and the trace FIFO
The ability to always match the contents of the memory with the contents of the internal instruction register has the effect of making it possible to emulate operations similar to those in actual use.

Moreover, the offset output terminal only requires 3 bits when prefetching 8 bytes, for example, so the number of terminals is much smaller than when outputting both the address of the currently executing instruction and the prefetch address to the outside of the chip. It's fine.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, emulation is used.

During execution, the prefetch address is output on the address bus, but in emulation execution mode, the address of the instruction being executed is output on the address bus, and the prefetch address is externally output based on this address and offset FST. An address may also be formed.

In the above description, the invention made by the present inventor was mainly applied to microcomputers, which is the background field of application, but the present invention is not limited thereto, and can be applied to general program-controlled data processing devices.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in a microcomputer having an instruction register capable of loading a plurality of instructions in advance, it becomes possible to perform emulation with operations similar to those in actual use.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention applied to a microcomputer, and FIG. 2 is a block diagram showing the main parts of the system configuration when emulating the microcomputer. 1... Micro ROM, 2... Control decoder. 3...Instruction register (FI F○ memory), 4...
...Micro address generation circuit, 6..Execution unit, 7..Memory access control circuit, 8..
Address bus, 9... Data bus, 11100. Subtraction circuit, DBR...read data buffer, VB
W...Write data buffer, REG. ~REGn...Temporary register, ALU...
- Arithmetic logic unit, PC...program counter, PFP...prefetch pointer, 21.22
... FIFO memory, 23... selection circuit. Figure 2 crθ

Claims (1)

[Claims] 1. An instruction register capable of fetching and holding a plurality of instructions in advance, and a signal indicating the difference between the address of the instruction being executed and the prefetch address for fetching the instructions in advance. and a data processing device, wherein a control signal for invalidating the instruction prefetched in the instruction register can be outputted to the outside. 2. A register that holds the address of the instruction being executed, a register that holds the prefetch address, and a subtraction circuit that calculates the difference between the address of the instruction that is being executed and the prefetch address based on the contents of these registers. 2. A data processing device according to claim 1, characterized in that said data processing device is provided with:.