JPH036597B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a dynamic integrated circuit device;
In particular, the present invention relates to a dynamic integrated circuit device that allows continuous tests involving fluctuations in power supply voltage from high voltage to low voltage to be successfully performed.

[Prior art]

FIG. 1 is a circuit diagram showing a conventional dynamic integrated circuit device, and shows an example of a dynamic flip-flop circuit often used in preamplifiers and the like. In the figure, Q ₁ to _{Q 8} are MOS transistors, C ₁ and C ₂ are MOS capacitors, and φ ₁ is the second
₂ is the clock shown in FIG. 2e, _φ3 is the clock shown in FIG. 2b, _N1 and _N2 are bootstrap terminals, I/O and O is a precharge line.

Next, the operation of the dynamic integrated circuit device having the above structure will be explained with reference to FIGS. 2a to 2e. First, at time t ₀ , the precharge line I/
Precharge O and /O. Thereafter, an "H" level signal is transmitted to the precharge line I/O as shown by the solid line in FIG. 2a, and an "L" level signal is transmitted to the precharge line /O as shown by the dotted line in FIG.
When a level signal is transmitted, the potential of this precharge line /O decreases to some extent. On the other hand, since the clock _φ3 becomes high level at time _t1 , the precharge line /O is forcibly sensed to a low level at high speed.
At this time, the precharge line I/O which is at a high level
is also pulled in to some extent and falls below the Vcc level.Next, at time _t2 , _the clock _φ1 goes to a high level as shown in FIG _. As shown by the solid line in FIG. 2c, the voltage at the precharge line I/O is increased to more than Vcc+V _T through the MOS transistor _Q1 , so that a so-called recharge effect is performed in which a voltage at the Vcc level appears on the precharge line I/O through the MOS transistor Q1. here,
V _T is the threshold voltage of the MOS transistor. Next, at time t ₃ , the clock φ ₁ is set to d in FIG.
The clock φ ₂ becomes a high level as shown in FIG. 2e, and the clock φ ₃ becomes a low level as shown in FIG. 2b.
Equalization of bootstrap terminals _N1 and _N2 and precharge of precharge lines I/O and /O are performed.

However, conventional dynamic integrated circuit devices malfunction as shown below when the power supply voltage changes from a high voltage (Vcc(H)) to a low voltage (Vcc(L)). In other words, regarding this malfunction, see Figure 3a.
~Explained with reference to FIG. 3f. First, at time t ₀ , during precharging of precharge lines I/O and /O, the power supply voltage changes from voltage (Vcc(H)) to voltage (Vcc(L)) as shown in Figure 3a. , precharge lines I/O and /O change accordingly as shown by solid lines and dotted lines in FIG. 3b, respectively, and clock φ ₂ also changes accordingly as shown in FIG. 3f. However, the potential of bootstrap terminals N ₁ and N ₂ is such that transistors Q ₃ and Q ₄ are in the cut-off state.
A high voltage of Vcc(H)−V _T remains. Next, at time _t1 , an "H" level signal is transmitted to the precharge line I/O as shown by the solid line in Figure 3b, and the precharge line /O is transmitted as shown by the dotted line in Figure 3b. When an "L" level signal is transmitted to the precharge line /O, the potential of the precharge line /O is slightly lowered. On the other hand, the clock _φ3 becomes high level as shown in FIG. 3c, and senses the precharge line /O to a low level at high speed. Next, at time _t2 , the clock _φ1 rises as shown in FIG. 3e, and a reprecharge action is performed to bring the precharge line I/O to the Vcc(L) level. Next, at time _t3 , clock _φ2 goes to a low level as shown in FIG. 3e, clock _φ3 goes to a high level as shown in FIG. 3f, and clock _φ3 goes to a low level as shown in FIG. When going low as shown, the bootstrap terminals N ₁ and N ₂
Equalization, precharge line I/O and I/O precharge are performed. At this time,
The voltages at bootstrap terminals _N1 and ₂ are equalized through transistor _Q7 , while at the same time bootstrap terminal _N2 is connected to the precharge line/
Since it is precharged through O and transistor _Q4 , transistor _Q7 is cut off, and sufficient equalization is not performed. That is, a high voltage near Vcc(H) - V _T is applied to bootstrap terminal _N1 , and a high voltage near Vcc(H) - V T is applied to bootstrap terminal _N2 .
This means that the low voltage of Vcc(L)−V _T is precharged. After this, in the next cycle, when the "L" signal is given to the precharge line I/O and the "H" signal is transmitted to the precharge line /O, the precharge line I/O potential decreases somewhat, but the boot Bootstrap terminal _N2 is connected to strap terminal _N1 .
Since the higher voltage remains, the transistor
Since the precharge line I/O is kept at a higher level than the precharge line /O through _Q1 , an accurate signal cannot be transmitted.If high-speed sensing is performed by clock _φ3 after this, the precharge line will be held at a higher level than the precharge line /O. If the I/O is set to a high level and the precharge line is set to a low level, a malfunction will occur. In fact, in testing dynamic circuit devices, when continuous tests are conducted in which the power supply voltage fluctuates from about 7V to about 4V in order to check the operating margin of the circuit, there is a drawback that malfunctions occur due to the above-mentioned causes.

[Summary of the invention]

Therefore, the purpose of the present invention is to sufficiently equalize the bootstrap terminal.
It is an object of the present invention to provide a dynamic integrated circuit device that can successfully perform continuous tests involving fluctuations in power supply voltage.

In order to achieve this object, the present invention sufficiently equalizes the bootstrap terminal using a bootstrapped signal, and will be described in detail below using embodiments.

[Embodiments of the invention]

FIG. 4 is a circuit diagram showing an embodiment of the dynamic integrated circuit device according to the present invention. In the figure, _φ4 is a clock bootstrapped to a voltage higher than Vcc+V _T as shown in FIG. 5f, and this clock _φ4 is applied to the gate of transistor _Q7 .

Next, the operation of the dynamic integrated circuit device having the above structure will be explained with reference to FIGS. 5a to 5f. First, when the precharge lines I/O and I/O are precharging and the power supply voltage changes from Vcc (H) to Vcc (L) at time t ₀ , the precharge line I/O follows this voltage change. The potential is also Vcc(L) as shown by the solid line in FIG. 5b, the potential of the precharge line/O is also Vcc(L) as shown by the dotted line in FIG. 5b, and the potential of the clock _φ4 is also Vcc(L) as shown in FIG. As shown in f, it changes to Vcc(L) and -V _T , respectively. However, the potentials of the bootstrap terminals _N1 and _N2 are at a high voltage of Vcc(H)-V _T as shown in FIG. 5d. On the other hand, since the clock _φ3 becomes high level at time _t1 , the precharge line /O is forcibly sensed to a low level at high speed. At this time, the precharge line I/O, which is at a high level, is also pulled in to some extent and falls below the Vcc level, so at the subsequent time _t2 , the clock _φ1 becomes a high level as shown in FIG. 5e,
The potential of the bootstrap terminal _N1 is the combination of the MOS capacitor _C1 , and as shown by the solid line in Figure 5d, the potential of the bootstrap terminal N1 is Vcc(L)+
In order to boost the voltage above V _T , the pre-charge line I/O
A voltage at the Vcc (L) level appears through the MOS transistor _Q1 . A so-called recharge effect is performed. Next, at time _t3 , clock _φ1 is at the fifth
As shown in figure e, it becomes low level and the clock _φ4
becomes a high level higher than Vcc(L)+V _T as shown in FIG. 5f, and the clock _φ3 becomes a low level as shown in _{FIG .} Precharge lines I/O and /O are precharged. Here, the bootstrap terminal _N2 is the precharge line/
O, is precharged through transistor _Q4 , but the potential reached is Vcc(L) - V _T , so
Transistor Q ₇ is not cut off and the potential at bootstrap terminals N ₁ and N ₂ is half the sum of the potentials at bootstrap terminals N ₁ and N ₂ (Vcc(H) + Vcc(L) - 2V _T )/ It will be equalized to 2. Therefore, after this, when an "L" signal is transmitted to the precharge line I/O and an "H" signal is transmitted to the precharge line /O, the precharge line I/O is sensed at a low level and the precharge line /O is sensed at a high level. Normal operation occurs. Strictly speaking, when the bootstrap terminal is equalized, the potential of the bootstrap terminal _N2 rises, so there is a possibility that the transistor _Q7 will be cut off. (7V to 4V) There is no problem at all.

FIG. 6 is a circuit diagram showing another embodiment of the dynamic integrated circuit device according to the present invention. In the figure, _φ5 is the power supply voltage level clock,
This is a clock that rises to a high level earlier than the precharge of precharge lines I/O and /O.

This embodiment circuit also operates in the same manner as shown in Fig. 4, and even in tests involving fluctuations in the power supply voltage, the voltages at the bootstrap terminals _{N1 and N2} are equalized by precharging the bootstrap terminal N2. is performed first, sufficient equalization is performed and normal operation is possible.

FIG. 7 is a circuit diagram showing still another embodiment of the dynamic integrated circuit device according to the present invention. In the figure, _φ6 is a clock synchronized with clock _φ2 and bootstrapped to a level higher than Vcc+ _VT , as shown in FIG. 8b. It goes without saying that this embodiment circuit also operates in the same manner as shown in FIG.
When the power supply voltage changes from Vcc (H) to Vcc (L) at time t ₀ while O and /O are precharging, the precharge lines I/O, /O, clock φ ₂ and clock φ ₆ also change to the 8th clock. Figure c, 8th
It changes accordingly as shown in Figures g and 8b. And the precharge lines I/O and /O are Vcc
(L), the voltage of the clock _φ6 becomes higher than Vcc(L)+ _VT , so the voltages of the bootstrap terminals _N1 and _N2 are discharged from Vcc(H) to Vcc(L). Thereafter, an "H" signal is transmitted to the precharge line I/O, and an "L" signal is transmitted to the precharge line I/O, high-speed sensing is performed by the clock _φ3 , and recharging is performed by the clock _φ1 . Furthermore, after that, clock _φ1 is at a low level, clock _φ2 is at a high level, and clock _{φ3 is} at a low level.
becomes low level, equalization of bootstrap terminals _N1 and _N2 , precharge lines I/O and /O are performed, and normal operation is performed.

Although this embodiment shows an example in which the bootstrap terminals are separated, it is of course possible to equalize and precharge the bootstrap terminals using a bootstrapped signal of Vcc+V _T or higher.

FIG. 9 is a circuit diagram showing still another embodiment of the dynamic integrated circuit device according to the present invention. In the figure, Q ₉ to Q ₁₁ are MOS transistors.

It goes without saying that the operation is similar to that shown in FIG. 4.

〔Effect of the invention〕

As described above in detail, according to the dynamic integrated circuit device according to the present invention, the bootstrap terminal is sufficiently equalized, so that tests involving fluctuations in the power supply voltage can be performed normally.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a conventional dynamic integrated circuit device, Figures 2a to 2e, and Figures 3a to 3.
3f is a diagram showing the waveforms of each part in FIG. 1, FIG. 4 is a circuit diagram showing an embodiment of the dynamic integrated circuit device according to the present invention, and FIGS.
FIG. f is a diagram showing waveforms of various parts in FIG. 4, FIGS. 6, 7, and 9 are circuit diagrams showing other embodiments of the dynamic integrated circuit device according to the present invention, and FIGS. FIG. 8g is a diagram showing waveforms at various parts in FIG. 7. Q ₁ ~QQ ₁₁ ...MOS transistors, C ₁ and C ₂ ...
...MOS capacitance, φ ₁ to φ ₆ ... clock, N ₁ and
N ₂ ...Bootstrap terminal, I/O and I/O...precharge line. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a dynamic integrated circuit device having a dynamic flip-flop circuit equipped with a pair of putotstrap terminals, it is provided that the putotstrap terminals are sufficiently equalized by a putotstrap signal. Dynamic integrated circuit device with special features. 2. The dynamic integrated circuit device according to claim 1, wherein the bootstrap terminal has its precharge delayed from the equalization of the bootstrap terminal. 3. The dynamic integrated circuit device according to claim 1, wherein the putot strap terminal has its precharge at the power supply voltage level. 4. The dynamic integrated circuit according to claim 1, wherein the bootstrap terminal is precharged and equalized by a bootstrapped signal.