JPH0366117A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the alignment of electron beams for which a complicated process is not required without causing alignment marks to be damaged in an etching process by irradiating a resist layer that is formed on the alignment marks prior to performance of the development process of the resist layer with electron beams which are enough to form each negative type pattern. CONSTITUTION:Prior to performance of an alignment process, a resist layer 5 on alignment marks 2 is irradiated sufficiently with electron beams. Then, positions of the alignment marks are retrieved by scanning over the alignment marks with the electron beams. Thereafter, patterns corresponding to aluminum electrode and wiring to be formed are described on the resist layer 5 with the electron beams and developed. An aluminum layer is etched by using the resist layer 5 in which the patterns are formed as a mask and then, the electrode and wiring 41 consisting of aluminum are formed. In the case where even a positive resist is used, it is changed into negative one and the resist layer 5 is left as it is. As a result, the alignment marks 2 are protected in an etching process.

Description

Detailed Description of the Invention [Summary] Regarding the improvement of the electron beam alignment method in the etching process using the electron beam exposure method, the alignment mark used in the alignment process in the electron beam exposure process is damaged during the etching process. Provides an electron beam alignment method that does not require complicated processes, allows for reuse in subsequent processes, prevents residue from being generated from alignment marks, and does not require complicated processes. With the aim of In a method for manufacturing a semiconductor device, which includes an etching step in the next step, using an alignment method that searches for an alignment mark, prior to the resist layer development step, a negative is applied to the resist layer formed on the alignment mark. It is configured to irradiate an electron beam sufficient to form a mold pattern.

[Industrial application field]

The present invention relates to an improved method of electron beam positioning in an etching process using electron beam exposure.

The position of the alignment mark is searched and alignment is performed.

See FIGS. 3 and 4 FIG. 3 is a plan view showing an example of the alignment mark 2 having a step, and FIG. 4 is a cross-sectional view taken along the line AA.

Generally, the alignment mark 2 is formed on the scribe line of the semiconductor wafer 1 using a polycrystalline silicon layer, an aluminum layer, or the like.

[Conventional technology]

A resist layer used in the etching process is formed on the layer to be etched formed on the semiconductor wafer, and when a pattern is drawn on this resist layer using an electron beam exposure device, the semiconductor wafer is It is necessary to accurately align the mutual position with other patterns formed above. Therefore, an alignment mark with a step is provided on the semiconductor wafer, and a secondary electron signal obtained by scanning the mark with an electron beam is detected.[Problem to be solved by the invention] Figures 5, 6, and Refer to Figure 7. A positive type resist has the property of being reversed to a negative type when overexposed and remaining after development. Therefore, regardless of whether a positive or negative resist layer is formed on the alignment mark, the overexposed area where the electron beam is scanned to search for the alignment mark, for example, the area indicated by 3 in FIG. In some cases, a resist layer remains after development. Therefore, the sixth
As shown in the BB cross-sectional view of FIG. 5, in the next etching step, the layer 4 to be etched remains on the alignment mark 2 in the area covered by the resist layer 5.
Etched layer 4 in areas not covered by resist layer 5
is removed to expose the alignment mark 2 and damage the alignment mark. Further, as shown in the cross-sectional view taken along the line C--C in FIG. 5 shown in FIG. 7, residues of the layer to be etched 4 remain on the side wall of the stepped portion of the alignment marr 2.

Note that as a method for preventing damage to alignment marks, the following method is disclosed in Japanese Patent Laid-Open No. 135578/1983. After scanning an electron beam over an alignment mark coated with a positive resist to achieve positioning, the electron beam is irradiated with appropriate exposure onto the positive resist layer in a region covering the alignment mark. When this is developed, the positive resist layer in the area scanned by the electron beam for alignment is reversed to a negative resist layer and remains, and the positive resist layer in the area covering other alignment marks is removed. . A metal layer is then deposited and lifted off to form a metal layer in areas covering the alignment marks, protecting them during the subsequent etching process. but,
This method requires metal vapor deposition and lift-off steps, which complicates the process, and also has the disadvantage that negative resists cannot be used.

The purpose of the present invention is to eliminate these drawbacks,
The alignment marks used in the alignment process in the electron beam exposure process are not damaged in the etching process, making it possible to use them again in the next process and beyond, and no residue is generated from the alignment marks. The object of the present invention is to provide an electron beam alignment method that does not require complicated steps.

[Means to solve the problem]

The above purpose is to align alignment marks with steps (2)
A resist layer (5) to be used in the next etching process is placed on the semiconductor wafer (1) on which
) and etching the formed alignment mark (2) of the resist layer (5) in the next step using a positioning method in which the formed alignment mark (2) is searched by scanning an electron beam. The method includes, prior to the step of developing the resist layer (5), irradiating the resist N (5) formed on the alignment mark (2) with an electron beam sufficient to form a negative pattern. This is achieved by a method for manufacturing a semiconductor device.

[Effect]

In the electron beam alignment method according to the present invention, when the resist layer on the alignment mark is sufficiently irradiated with an electron beam, specifically, when the electron beam is irradiated to an extent sufficient to form a negative pattern, in the case of a negative resist, Of course, even in the case of a positive type resist, it is reversed to a negative type and a resist layer remains on the alignment mark after development.

Therefore, in the next etching process, the alignment mark is protected by the resist layer and the layer to be etched formed below it, and is not damaged, and no residue is generated at the step of the alignment mark. It also disappears.

Therefore, this alignment mark can be used again in the next process and thereafter.

〔Example〕

Hereinafter, a positioning process in an electron beam exposure process according to an embodiment of the present invention will be described with reference to the drawings.

For example, a case will be described in which electrodes and wiring made of aluminum are formed on a silicon wafer on which electrodes and wiring made of polycrystalline silicon are formed, with an insulating film such as PSG interposed therebetween. Note that when forming electrodes and wiring made of polycrystalline silicon, alignment marks as shown in FIG. 3 are simultaneously formed between each chip on the scribe line.

Referring to FIG. 2, a 150 layer 6, an aluminum layer 4, and a resist layer 5 are sequentially formed on a semiconductor wafer 1 on which an electrode/wiring 7 made of polycrystalline silicon and an alignment mark 2 are formed. Prior to drawing a pattern corresponding to the aluminum electrodes/wirings on the resist layer 5 using an electron beam exposure device, the electrodes/wirings 7 made of polycrystalline silicon that have already been formed and the aluminum electrodes/wirings to be formed are drawn on the resist layer 5. Align the electrodes and wiring.

Prior to the alignment process, the resist layer 5 on the alignment mark 2 is sufficiently irradiated with an electron beam.

As a result, if a positive resist is used, it is converted to a negative resist.

Refer to FIG. 1 Next, after scanning the alignment mark 2 with an electron beam to search for its position and aligning it, a pattern corresponding to the electrodes and wiring made of aluminum to be formed is placed on the resist layer 5 using an electron beam. Draw with a beam and develop. The aluminum layer 4 is etched using the patterned resist layer 5 as a mask to form electrodes/wirings 41 made of aluminum. At this time, not only when a negative type resist is used, but also when a positive type resist is used, the resist layer 5 is converted to a negative type and remains on the alignment mark 2. The alignment mark 2 is protected during the process. Note that the step of irradiating the alignment mark region with an electron beam does not necessarily need to be performed before the alignment step, and may be performed after the alignment step.

〔Effect of the invention〕

As explained above, in the method for manufacturing a semiconductor device according to the present invention, the resist layer formed on the alignment mark for alignment is irradiated with an electron beam sufficient to form a negative pattern. Since the resist layer remains on the mark, the alignment mark will not be damaged in the next etching process, and no residue will be generated on the alignment mark, making it possible to use this alignment mark again in the next process. It becomes possible to do so.

[Brief explanation of drawings]

1 and 2 are process diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3 is a plan view showing one example of the alignment mark. FIG. 4 is a sectional view taken along the line AA in FIG. 3. FIG. 5 is a plan view showing the exposure area during alignment. FIG. 6 is a sectional view taken along line BB in FIG. 5 after etching. FIG. 7 is a sectional view taken along line CC in FIG. 5 after etching. DESCRIPTION OF SYMBOLS 1...Semiconductor wafer, 2...Alignment mark, 3...Positioning exposure area, 192 Etched layer (argonium layer), aluminum electrode/wiring, resist layer, insulating film, polycrystalline silicon Electrodes/wiring.

Claims (1)

[Claims] A resist layer (5) to be used in an etching process to be performed in the next process is formed on a semiconductor wafer (1) on which an alignment mark (2) having a step is formed, and the resist layer (5) Alignment mark formed (
2) In the method for manufacturing a semiconductor device, the method includes etching in the next step using an alignment method of scanning and searching with an electron beam, in which the alignment mark is removed prior to the step of developing the resist layer (5). (2) A method for manufacturing a semiconductor device, comprising the step of irradiating the resist layer (5) formed thereon with an electron beam sufficient to form a negative pattern.