JPH0366119A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0366119A
JPH0366119A JP1203006A JP20300689A JPH0366119A JP H0366119 A JPH0366119 A JP H0366119A JP 1203006 A JP1203006 A JP 1203006A JP 20300689 A JP20300689 A JP 20300689A JP H0366119 A JPH0366119 A JP H0366119A
Authority
JP
Japan
Prior art keywords
resin film
film
film pattern
organic resin
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1203006A
Other languages
Japanese (ja)
Inventor
Eiichi Kawamura
栄一 河村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1203006A priority Critical patent/JPH0366119A/en
Publication of JPH0366119A publication Critical patent/JPH0366119A/en
Pending legal-status Critical Current

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  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To form with high accuracy a multilayer resin film pattern which has few defects by restricting the remaining film thickness of a lower organic resin film and determining the film thickness of an upper organic resin film while joining its upper film with the lower film when the surface of an intermediate metallic resin film pattern is exposed to the outside in the process of dry- etching of the lower organic resin film after making patterns of the upper organic resin film and the intermediate metallic resin film act as masks. CONSTITUTION:A lower resist film 3 is etched by employing patterns 5' and 4' of an upper resist film and an intermediate SOG film as masks and applying an RIE process in which a CF4 gas is used instead of an O2 gas. In such an etching process, even an upper resist film pattern 5' is etched simultaneously and when the surface of the intermediate SOG film pattern 4' is exposed, the residual film thickness of the lower resist film 3 comes to 1.0mum. Subsequently, when the residual film thickness (h) of the resist film 3 is etched by making the above SOG film pattern 4' to act as a mask, a lower resist film pattern 3' is formed. Since the remaining film thickness of the above film 3 does not exceed 1.0mum, occurrence of defects in the pattern is suppressed to a minimum.

Description

【発明の詳細な説明】 〔概 要〕 本発明は多層樹脂膜パターン形成方法に関し、欠陥の少
ない多層樹脂膜パターンを高精度で形成することを目的
とし、 薄膜の形成された基板上に下層有機樹脂膜、中間層金属
樹脂膜、上層有機樹脂膜を順次形成し、ついでフォトリ
ソグラフィにより上層有機樹脂膜パターンを形成し、つ
いで該上層有機樹脂膜パターンをマスクとしてドライエ
ツチングを行い中間層金属樹脂膜パターンを形成し、つ
いで該上層有機樹脂膜パターン及び該中間層金属樹脂膜
パターンをマスクとしてドライエツチングを行い下層有
機樹脂IlΔパターンを形成し、該下層有機樹脂j模パ
ターンをマスクとして該薄膜をエツチングする工程を有
する半導体装置の製造方法であって、該上層有機樹脂膜
パターン及び該中間層金属樹脂膜パターンをマスクとし
て該下層有機樹脂膜をドライエツチングする過程で、該
上層有機樹脂膜パターンがエツチング除去され該中間層
金属樹脂膜パターンの表面が露出したとき、該下層有機
樹脂膜の残り膜厚が1μmを越えないように該上層有機
樹脂膜の膜厚を設定するように構成する。
[Detailed Description of the Invention] [Summary] The present invention relates to a method for forming a multilayer resin film pattern, and aims to form a multilayer resin film pattern with few defects with high precision. A resin film, an intermediate layer metal resin film, and an upper layer organic resin film are sequentially formed, and then an upper layer organic resin film pattern is formed by photolithography, and then dry etching is performed using the upper layer organic resin film pattern as a mask to form an intermediate layer metal resin film. A pattern is formed, and then dry etching is performed using the upper organic resin film pattern and the intermediate metal resin film pattern as masks to form a lower organic resin IlΔ pattern, and the thin film is etched using the lower organic resin pattern as a mask. A method for manufacturing a semiconductor device comprising the step of dry etching the lower organic resin film using the upper organic resin film pattern and the intermediate metal resin film pattern as masks, in which the upper organic resin film pattern is etched. The thickness of the upper organic resin film is set so that when the surface of the intermediate metal resin film pattern is exposed after removal, the remaining thickness of the lower organic resin film does not exceed 1 μm.

〔産業上の利用分野〕[Industrial application field]

本発明は多層樹脂膜パターン形成方法に係り、特に多層
レジスト膜パターン形成方法に関する。
The present invention relates to a method for forming a multilayer resin film pattern, and more particularly to a method for forming a multilayer resist film pattern.

半導体素子を形成すべき基板上には通常凹凸が存在する
ため直接この上に形成したレジストの膜厚は不均一とな
る。従って通常のフォトリソグラフィでは露光の過不足
が生じて高精度のレジストパターンを得ることはできな
い。多層レジストパターン形成方法はこのような問題を
避4ノるため用いられる方法であり、基板」二のpH凸
と無関係にパターン精度を維持できるため高密度ICの
パターニングに適している。しかし、形成工程が複雑な
こともあってパターンに欠陥が生しやすくその改善が望
まれている。
Since there are usually irregularities on a substrate on which a semiconductor element is to be formed, the thickness of a resist formed directly on the irregularities becomes non-uniform. Therefore, in normal photolithography, overexposure and underexposure occur, making it impossible to obtain a highly accurate resist pattern. The multilayer resist pattern forming method is a method used to avoid such problems, and is suitable for patterning high-density ICs because pattern accuracy can be maintained regardless of the pH convexity of the substrate. However, since the formation process is complicated, defects are likely to occur in the pattern, and improvements are desired.

〔従来の技術〕[Conventional technology]

第5図は従来の多層レジストを用いたパターン形成工程
を説明するための断面図である。同図(a)に示すよう
に、半導体基板1上にパターニングすべき薄膜例えば前
照2を形成し、この上にまず有機樹脂からなる下層レジ
スト膜3を塗布する。酎膜2の表面に存在する凹凸(図
示せず)は、下層レジスト膜3の膜厚を充分厚くするこ
とによって平坦化する。次に、この平坦化された下層レ
ジスト膜3上に薄くかつ均一な金属樹脂膜からなる中間
層SOG (スピンオングラス)膜4、有機樹脂からな
る上層レジスト膜5を順次塗布する。ついで同図(b)
に示すように、通常のフォトリソグラフィにより上層レ
ジスト膜パターン5′を形成する。
FIG. 5 is a cross-sectional view for explaining a pattern forming process using a conventional multilayer resist. As shown in FIG. 2A, a thin film to be patterned, for example, a front film 2, is formed on a semiconductor substrate 1, and a lower resist film 3 made of an organic resin is first applied thereon. The unevenness (not shown) existing on the surface of the thin film 2 is flattened by making the lower resist film 3 sufficiently thick. Next, on this flattened lower resist film 3, a thin and uniform intermediate layer SOG (spin-on glass) film 4 made of a metal resin film and an upper resist film 5 made of an organic resin are sequentially applied. Then the same figure (b)
As shown in FIG. 2, an upper resist film pattern 5' is formed by ordinary photolithography.

上層レジスト膜5を前述のように薄くかつ均一な膜厚と
することにより高精度のパターニングが可能である。つ
いで同図(C)に示すように、上層レジスト膜パターン
5′をマスクにし02系ガスを流して反応性イオンエツ
チング(RIE)を行い中間層SOG膜パターン4′を
形成する。ついで上層レジスト膜パターン5′及び中間
層SOG膜パターン4′をマスクにして弗素系ガスを流
してRIE法により下層レジスト膜3のエツチングを行
う。
By making the upper resist film 5 thin and uniform in thickness as described above, highly accurate patterning is possible. Next, as shown in FIG. 5C, using the upper resist film pattern 5' as a mask, reactive ion etching (RIE) is performed by flowing 02 gas to form an intermediate SOG film pattern 4'. Next, the lower resist film 3 is etched by RIE using the upper resist film pattern 5' and the intermediate SOG film pattern 4' as masks and flowing a fluorine gas.

上記エツチング工程では、上層レジスト膜5と下層レジ
スト膜3はC,Hを含む同種の有機樹脂膜であるためエ
ツチングの選択性がない。しかもパターン精度向上のた
め上層レジスト膜パターン5′の膜厚は前述したように
下層レジスト膜3の膜厚に比べて通常はかなり薄く設定
する。そのため同図(d)に示すように上層レジスト膜
パターン5′がエツチング除去されて中間層SOG膜パ
ターン4′の表面が露出したときにはまだ下層レジスト
膜3のエンチングは終了せず、残/JH#、厚りが存在
することになる。
In the above etching step, since the upper resist film 5 and the lower resist film 3 are the same type of organic resin films containing C and H, there is no etching selectivity. Furthermore, in order to improve pattern accuracy, the thickness of the upper resist film pattern 5' is usually set to be much thinner than the thickness of the lower resist film 3, as described above. Therefore, when the upper resist film pattern 5' is etched away and the surface of the intermediate SOG film pattern 4' is exposed, as shown in FIG. , there will be a thickness.

その後、さらに中間層5OGI模パターン4′をマスク
にして下層レジスト膜のり曳り膜厚11のエツチングを
行うと、同図(e)に示すように下層レジスト膜パター
ン3′が形成される。しかる後、下層レジスト膜パター
ン3′をマスクにしてAI膜2をエツチングする。
Thereafter, by etching the lower resist film to a thickness of 11 using the intermediate layer 5 OGI model pattern 4' as a mask, a lower resist film pattern 3' is formed as shown in FIG. 3(e). Thereafter, the AI film 2 is etched using the lower resist film pattern 3' as a mask.

〔発明が解決しようとする課題] しかしながら実際に上記の方法を用いた場合、第5図(
e)に示したように、AI膜膜上上下層レジスト膜の残
滓7が観測される。その原因は以下のように考えられる
。即ち、第5図(d)に見られるように、中間層SOG
膜パターン4′をマスクにして下層レジスト膜3をRI
E法によりエツチングすに際、基板側に存在するセルフ
バイアスによりプラズマ中のイオンが基板に向かって加
速され、金属樹脂からなる中間層SOG膜中のSiある
いはSi酸化物がスパッタされ、その結果生したSOG
膜の残滓6がエツチング途中の下層レジストnM3の表
面に被着し、これがマスクとなって下層レジスト膜の残
滓7が残るものである。このような残滓は次に下層レジ
スト膜パターン3′をマスクにして^1膜2のパターニ
ングを行う際、へ119に対するエツチングのマスクと
して機能し、その結果、A1膜パターンに欠陥が生しる
。
[Problem to be solved by the invention] However, when the above method is actually used, the problem shown in Fig. 5 (
As shown in e), residues 7 of the upper and lower resist films are observed on the AI film. The reason for this is thought to be as follows. That is, as shown in FIG. 5(d), the intermediate layer SOG
RI the lower resist film 3 using the film pattern 4' as a mask.
When etching using the E method, ions in the plasma are accelerated toward the substrate by the self-bias that exists on the substrate side, and Si or Si oxide in the intermediate layer SOG film made of metal resin is sputtered, resulting in SOG
The film residue 6 adheres to the surface of the lower resist nM3 during etching, and this serves as a mask, leaving a residue 7 of the lower resist film. Such residue functions as an etching mask for the layer 119 when patterning the ^1 film 2 using the lower resist film pattern 3' as a mask, resulting in defects in the A1 film pattern.

以上のようなパターンの欠陥を低減するためには、基板
側のセルフバイアスを下げて中間層SOG膜がスパッタ
されること自体を防くか、あるいは中間層SOG膜パタ
ーン4′の表面が露出しないように上層レジスト膜5の
膜厚を厚くすればよい。しかし一方、前に述べたように
」二層レジスト膜5を通常のフォトリソグラフィで正確
にパターニングするためにはその膜厚を出来るだけ薄く
する必要がある。即ち、パターンの欠陥を少なくするこ
ととパターニング精度を向上させることとは上層レジス
I−膜の膜厚に相反する条件を課すものであるが、従来
は上層レジスト膜の膜厚は経験的に決められ、最適化さ
れていなかった。
In order to reduce the pattern defects described above, it is necessary to lower the self-bias on the substrate side to prevent the intermediate layer SOG film from being sputtered, or to prevent the surface of the intermediate layer SOG film pattern 4' from being exposed. The thickness of the upper resist film 5 may be increased as shown in FIG. On the other hand, as stated above, in order to accurately pattern the two-layer resist film 5 by ordinary photolithography, it is necessary to make the film thickness as thin as possible. In other words, reducing pattern defects and improving patterning accuracy impose contradictory conditions on the thickness of the upper resist film, but conventionally the thickness of the upper resist film has been determined empirically. was not optimized.

そこで本発明はバクーン欠陥が少なくかつ高精度の多層
樹脂膜パターンを形成する方法を提供することを目的と
する。
Therefore, an object of the present invention is to provide a method for forming a highly accurate multilayer resin film pattern with few Bakun defects.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題の解決は、薄膜の形成された基板上に下層有機
樹脂膜、中間層金属樹脂膜、上層有機樹脂膜を順次形成
し、ついでフォトリソグラフィにより上層有機樹脂膜パ
ターンを形成し、ついで該上層有機樹脂膜パターンをマ
スクとしてドライエツチングを行い中間層金属樹脂膜パ
ターンを形成し、ついで該上層有機樹脂膜パターン及び
該中間層金属樹脂膜パターンをマスクとしてドライエ・
ノチングを行い下層有機樹脂膜パターンを形成し、該下
層有機樹脂膜パターンをマスクとして該薄膜をエツチン
グする工程を有する半導体装置の製造方法であって、該
上層有機樹脂膜パターン及び該中間層金属樹脂膜パター
ンをマスクとして該下層有機樹脂膜をドライエツチング
する過程で、該上層有機樹脂膜パターンがエツチング除
去され該中間層金属樹脂膜パターンの表面が露出したと
き、該下層有機樹脂膜の残り膜厚が1μmを越えないよ
うに該上層有機樹脂膜の膜厚を設定したことを特徴とす
る半導体装置の製造方法、あるいは、薄膜の形成された
基板上に下層有機樹脂)1り、中間層金属樹脂膜、上層
有機樹脂膜を順次形成し、ついでフォトリソグラフィに
より上層有機樹脂膜パターンを形成し、ついで該上層有
機樹脂膜パターンをマスクとしてドライエツチングを行
い中間層金属樹脂膜パターンを形成した後、該上層有機
樹脂膜パターン及び該中間層金属樹脂膜パターンをマス
クとして磁界を印加した反応性イオンエツチングを行い
下層有機樹脂膜パターンを形成するか、あるいは、該上
層有機樹脂膜パターン及び該中間層金属樹脂膜パターン
をマスクとしてドライエツチングを行うことによって該
上層有機樹脂膜パターンがエツチング除去され該中間層
金属樹脂膜バタンの表面が露出した後に、磁界を印加し
た反応性イオンエツチングを行い下層有機樹脂膜パター
ンを形成し、該下層有機樹脂膜パターン(3′)を0 マスクとして該薄膜(2)をエツチングする工程を有す
ることを特徴とする半導体装置の製造方法によって達成
される。
The above problem can be solved by sequentially forming a lower organic resin film, an intermediate metal resin film, and an upper organic resin film on a substrate on which a thin film has been formed, and then forming an upper organic resin film pattern by photolithography. Dry etching is performed using the organic resin film pattern as a mask to form an intermediate layer metal resin film pattern, and then dry etching is performed using the upper layer organic resin film pattern and the intermediate layer metal resin film pattern as masks.
A method for manufacturing a semiconductor device comprising the steps of notching to form a lower organic resin film pattern, and etching the thin film using the lower organic resin film pattern as a mask, the method comprising: forming a lower organic resin film pattern using the upper organic resin film pattern and the intermediate metal resin layer; In the process of dry etching the lower organic resin film using the film pattern as a mask, when the upper organic resin film pattern is etched away and the surface of the intermediate metal resin film pattern is exposed, the remaining film thickness of the lower organic resin film is A method for manufacturing a semiconductor device, characterized in that the thickness of the upper organic resin film is set so that the film thickness does not exceed 1 μm, or a lower organic resin film is formed on a substrate on which a thin film is formed, or an intermediate metal resin film is formed on the substrate. A film and an upper organic resin film are sequentially formed, then an upper organic resin film pattern is formed by photolithography, and then dry etching is performed using the upper organic resin film pattern as a mask to form an intermediate metal resin film pattern. A lower layer organic resin film pattern is formed by performing reactive ion etching using the upper layer organic resin film pattern and the intermediate layer metal resin film pattern as masks and applying a magnetic field, or alternatively, the upper layer organic resin film pattern and the intermediate layer metal resin film pattern are etched. After dry etching is performed using the film pattern as a mask to remove the upper organic resin film pattern and expose the surface of the intermediate metal resin film button, reactive ion etching is performed with a magnetic field applied to remove the lower organic resin film pattern. This is achieved by a method of manufacturing a semiconductor device characterized by comprising the steps of: forming a thin film (2) using the lower organic resin film pattern (3') as a mask; and etching the thin film (2).

〔作 用〕[For production]

パターンに欠陥が生じる原因は第5図(d)に見られる
ように、金属樹脂からなる中間層SOG膜パターン4′
がスパッタされてその残滓6が有機樹脂からなる下層レ
ジスト膜3の残り膜厚り上に付着することに起因してい
る。従って下層レジスト膜の残り膜厚が薄いほど中間層
SOG膜のスパッタ時間が短くなり、その残滓は少なく
なると考えられる。本発明者は下層レジスト3の残り膜
厚に対して中間層SOG膜の残滓密度がどのように変化
するかについて実験を行った結果、第2図に示すような
データを得た。同図によれば、下層レジスト膜の残り膜
厚が1pI11以上を越えると中間層SOG膜の残滓密
度が急激に増加することを示している。
As shown in FIG. 5(d), the cause of defects in the pattern is the intermediate layer SOG film pattern 4' made of metal resin.
This is due to sputtering and the residue 6 adhering to the remaining thickness of the lower resist film 3 made of organic resin. Therefore, it is considered that the thinner the remaining film thickness of the lower resist film is, the shorter the sputtering time for the intermediate SOG film is, and the less the residue is. The inventor conducted an experiment to determine how the residual density of the intermediate layer SOG film changes with respect to the remaining film thickness of the lower resist layer 3, and as a result, data as shown in FIG. 2 was obtained. The figure shows that when the remaining thickness of the lower resist film exceeds 1 pI11 or more, the residual density of the intermediate SOG film increases rapidly.

以上のことから、下層レジスト膜の残り膜厚がll1m
を越えないように上層レジスト膜の膜厚を設定すること
によりパターン欠陥密度を小さくすることができ、同時
にパターン精度の劣化をも最小限に抑えることが可能と
なることがわかる。
From the above, the remaining film thickness of the lower resist film is 11 m.
It can be seen that by setting the thickness of the upper resist film so as not to exceed , it is possible to reduce the pattern defect density, and at the same time, it is possible to minimize deterioration in pattern accuracy.

また、本発明者は中間層SOG膜をRIE法によりエツ
チングする際、磁界を印加することによって中間層金属
樹脂膜の残滓密度が低減され、その結果パターン欠陥密
度が低減されることを見いだした。
Furthermore, the inventors have discovered that when etching the intermediate layer SOG film by the RIE method, by applying a magnetic field, the residual density of the intermediate layer metal resin film is reduced, and as a result, the pattern defect density is reduced.

第3図は磁界を印加するためのマグネットを有するRI
B装置の要部断面図であり、11はマグネット、12は
高周波電極、13は接地電極、14はエツチングすべき
基板、15は高周波電源である。同図には高周波電極1
2と接地電極13の間にプラズマを発生させたときの電
極間の電位分布を示しており、基板14には図中Vで示
したセルフバイアスが印加される。第4図には、上記R
IE装置に周波数13゜56 MHzの高周波電力20
0 Wを印加したときの基板14に加わるセルフバイア
スの磁界依存性を示したものである。同図から明らかな
ように、磁界を1 2 印加することによってセルフバイアスは低下する。
Figure 3 shows an RI with a magnet for applying a magnetic field.
This is a cross-sectional view of the main parts of apparatus B, in which 11 is a magnet, 12 is a high frequency electrode, 13 is a ground electrode, 14 is a substrate to be etched, and 15 is a high frequency power source. The figure shows high frequency electrode 1.
2 shows the potential distribution between the electrodes when plasma is generated between the substrate 14 and the ground electrode 13, and a self-bias indicated by V in the figure is applied to the substrate 14. In Figure 4, the above R
High frequency power with a frequency of 13°56 MHz is applied to the IE device.
This figure shows the magnetic field dependence of the self-bias applied to the substrate 14 when 0 W is applied. As is clear from the figure, the self-bias is reduced by applying a magnetic field of 1 2 .

即ち、磁界の印加はプラズマ中のイオンが基板側に加速
されて中間層SOG膜パターンを衝撃し下層レジスト膜
の残り膜厚上に飛散することを防ぐ上で効果があり、中
間層5OG19の残滓密度を減少させることができる。
In other words, the application of a magnetic field is effective in preventing ions in the plasma from being accelerated toward the substrate, impacting the intermediate layer SOG film pattern, and scattering onto the remaining thickness of the underlying resist film, thereby preventing the ions in the intermediate layer 5OG19 from being scattered. Density can be reduced.

このような現象はSOG膜以外の金属樹脂膜を用いた場
合にも生じるものである。
Such a phenomenon also occurs when a metal resin film other than the SOG film is used.

〔実施例〕〔Example〕

第1図は本発明の実施例を示す工程断面図である。 FIG. 1 is a process sectional view showing an embodiment of the present invention.

同図(a)に示すように、半導体基板l上にAI膜2を
形成し、ついで有機樹脂からなる下層レジスト膜3とし
てノボラック系のポジ型レジストを2μm、金属樹脂か
らなる中間層SOG膜4(例えば東京応化製OCD t
Vpe 2)を0.37ffi、有機樹脂からなる上層
レジスト膜5としてノボラック系のポジ型レジストを1
.57+m、順次塗布する。ついで同図(b)に示すよ
うに、通常のフォトリソグラフィにより上層レジスト膜
パターン5′を形成する。ついで同図(C)に示すよう
に1、上層レジスト膜パターン5′をマスクにしてRI
E法によりエツチングを行い、中間層SOG膜パターン
4′を形成する。上記エツチングは02ガスを3003
CCM流し、圧力を0゜03 Torrとし、周波数1
3.56 MHzのRF電力200Wを印加して行った
。このエツチング工程においては、上層レジスト膜5の
エツチングも進行し、その結果、上層レジスト膜パター
ン5′の膜厚は1.0−となった。ついで上層レジスト
膜パターン5′及び中間1soc膜パターン4′をマス
クにして02ガスに代えてCF、ガスを用いたRIE法
により下層レジスト膜3のエツチングを行った。
As shown in FIG. 5A, an AI film 2 is formed on a semiconductor substrate l, a novolak positive resist film 3 is used as a lower resist film 3 made of an organic resin, and a novolac positive type resist is applied to a thickness of 2 μm, and an intermediate SOG film 4 made of a metal resin is formed. (For example, Tokyo Ohka OCD t
Vpe 2) was 0.37ffi, and novolac positive type resist was used as the upper resist film 5 made of organic resin.
.. 57+m, applied sequentially. Then, as shown in FIG. 2B, an upper resist film pattern 5' is formed by ordinary photolithography. Next, as shown in the same figure (C), 1. RI is performed using the upper resist film pattern 5' as a mask.
Etching is performed using the E method to form an intermediate layer SOG film pattern 4'. The above etching uses 02 gas to 3003
CCM flow, pressure 0°03 Torr, frequency 1
This was done by applying 200 W of RF power at 3.56 MHz. In this etching process, etching of the upper resist film 5 also progressed, and as a result, the film thickness of the upper resist film pattern 5' became 1.0-. Next, using the upper resist film pattern 5' and the middle 1soc film pattern 4' as masks, the lower resist film 3 was etched by RIE using CF gas instead of 02 gas.

このエツチング工程では上層レジスト膜パターン5′も
同時にエツチングされ、中間層SOG膜パターン4′の
表面が露出した時点では同図(d)に示すように、下層
レジスト1li3の残り膜厚は1.07zmとなった。
In this etching process, the upper resist film pattern 5' is also etched at the same time, and when the surface of the intermediate SOG film pattern 4' is exposed, the remaining film thickness of the lower resist film 1li3 is 1.07 zm, as shown in FIG. It became.

さらに続けて中間層SOG膜パターン4′をマスクにし
て下層レジスト膜3の残り膜厚りのエツチングを行うと
、同図(e)に示すように下3 4 層レジスト膜パターン3′が形成される。
Further, by etching the remaining thickness of the lower resist film 3 using the intermediate layer SOG film pattern 4' as a mask, a lower 34-layer resist film pattern 3' is formed as shown in FIG. Ru.

以上の実施例において、中間層SOG膜パターン4′を
マスクとする下層レジス)・膜3のエツチングを行う際
、下層レジス1〜膜3の残り膜厚が1.0μmを越えて
いないため第2図からも明らかなようにパターンの欠陥
を最小限に抑えることができる。
In the above embodiment, when etching the lower layer resist 1 to film 3 using the intermediate layer SOG film pattern 4' as a mask, the remaining film thickness of the lower layer resist 1 to film 3 does not exceed 1.0 μm. As is clear from the figure, pattern defects can be minimized.

また、中間層SOG膜パターン4′をマスクとして下層
レジスト膜3をRIE法によりエツチングする際、第3
図に示ずRIE装置を用い100ガウスの磁界を印加す
ると、基板に加わるセルフバイアスは第4図に示すよう
に500 Vから約100 Vにまで低下し、その結果
、中間層SOG膜の残滓密度を従来に比べて大幅に低減
することができた。
Also, when etching the lower resist film 3 by RIE using the intermediate layer SOG film pattern 4' as a mask, the third
When a magnetic field of 100 Gauss is applied using an RIE device (not shown), the self-bias applied to the substrate decreases from 500 V to approximately 100 V as shown in Figure 4, and as a result, the residual density of the intermediate SOG film decreases. was able to be significantly reduced compared to conventional methods.

この方法によれば、下層レジスト膜3の残り膜厚が1.
0μmを越える場合にも、実用上問題の生しない程度に
中間層SOG膜の残滓密度を減少さ−I!−ることがで
きる。さらに、磁界を印加したエツチングは上層レジス
ト膜パターン5′及び中間層S○G膜パターン4′をマ
スクとして下層レジスト膜3を形成する段階から用いる
こともできる。
According to this method, the remaining film thickness of the lower resist film 3 is 1.
Even if it exceeds 0 μm, the residual density of the intermediate layer SOG film can be reduced to an extent that does not cause any practical problems. - can. Furthermore, etching with the application of a magnetic field can also be used from the stage of forming the lower resist film 3 using the upper resist film pattern 5' and the intermediate S○G film pattern 4' as masks.

(発明の効果〕 以上のように本発明によれば下層レジスト膜の残り膜厚
」二への中間層SOG膜の残滓の付着を最小限に抑える
ことができるため、欠陥の少ない高精度の多層レジスト
パターンを形成することが可能となる。
(Effects of the Invention) As described above, according to the present invention, it is possible to minimize the adhesion of the residue of the intermediate layer SOG film to the remaining film thickness of the lower resist film. It becomes possible to form a resist pattern.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例を示す工程断面図、第2図は下
層レジスト膜の残り膜厚と中間層SOG膜残滓密度との
関係を示す図、 第3図はtE装置の要部断面図、 第4図はセルフバイアスの磁界依存性を示す図、第5図
は従来例の問題点を示す工程断面図、である。 図において、 1 番よ基板、 2はA1膜、 5 6 3は下層レジスト膜、 3′は下層レジスト膜バクーン、 4は中間層SOC膜、 4′は中間層SOC膜パターン、 5は上層レジスト膜、 5′は上層レジスト膜パターン、 6は中間層SOC膜残滓、 7は下層レジスト膜残滓、 11はマグネット、 12ば高周波電極、 13は接地電極、 14は基板、 15は高周波電源、 hは下層レジスト膜の残り膜厚、 である。 鍔 少″ 103− 特開平3−66119(6) ワ O 0 00 セルフバイγヌの磁界依育11’l:と示す間第4 図 従来ブクリの間爬点と示す工程断面間 第 5 図 105−
Fig. 1 is a process cross-sectional view showing an embodiment of the present invention, Fig. 2 is a view showing the relationship between the remaining film thickness of the lower resist film and the intermediate layer SOG film residue density, and Fig. 3 is a cross-sectional view of the main part of the tE device. 4 is a diagram showing the magnetic field dependence of self-bias, and FIG. 5 is a process sectional view showing problems in the conventional example. In the figure, 1 is the substrate, 2 is the A1 film, 5 6 3 is the lower resist film, 3' is the lower resist film, 4 is the intermediate SOC film, 4' is the intermediate SOC film pattern, and 5 is the upper resist film. , 5' is the upper resist film pattern, 6 is the intermediate layer SOC film residue, 7 is the lower resist film residue, 11 is the magnet, 12 is the high frequency electrode, 13 is the ground electrode, 14 is the substrate, 15 is the high frequency power supply, h is the lower layer The remaining thickness of the resist film is: 103- JP-A-3-66119 (6) WaO 0 00 Magnetic field dependence of self-buy γnu 11'l: between Fig. 4 and process cross-section shown between the interposition point of conventional booklet and Fig. 5 Fig. 105-

Claims (2)

【特許請求の範囲】[Claims] (1)薄膜(2)の形成された基板(1)上に下層有機
樹脂膜(3)、中間層金属樹脂膜(4)、上層有機樹脂
膜(5)を順次形成し、ついでフォトリソグラフィによ
り上層有機樹脂膜パターン(5′)を形成し、ついで該
上層有機樹脂膜パターン(5′)をマスクとしてドライ
エッチングを行い中間層金属樹脂膜パターン(4′)を
形成し、ついで該上層有機樹脂膜パターン(5′)及び
該中間層金属樹脂膜パターン(4′)をマスクとしてド
ライエッチングを行い下層有機樹脂膜パターン(3′)
を形成し、該下層有機樹脂膜パターン(3′)をマスク
として該薄膜(2)をエッチングする工程を有する半導
体装置の製造方法であって、 該上層有機樹脂膜パターン(5′)及び該中間層金属樹
脂膜パターン(4′)をマスクとして該下層有機樹脂膜
(3)をドライエッチングする過程で、該上層有機樹脂
膜パターン(5′)がエッチング除去され該中間層金属
樹脂膜パターン(4′)の表面が露出したとき、該下層
有機樹脂膜(3)の残り膜厚が1μmを越えないように
該上層有機樹脂膜(5)の膜厚を設定したことを特徴と
する半導体装置の製造方法。
(1) A lower organic resin film (3), an intermediate metal resin film (4), and an upper organic resin film (5) are sequentially formed on the substrate (1) on which the thin film (2) has been formed, and then by photolithography. An upper layer organic resin film pattern (5') is formed, then dry etching is performed using the upper layer organic resin film pattern (5') as a mask to form an intermediate layer metal resin film pattern (4'), and then the upper layer organic resin film pattern (4') is formed. Dry etching is performed using the film pattern (5') and the intermediate metal resin film pattern (4') as a mask to form a lower organic resin film pattern (3').
and etching the thin film (2) using the lower organic resin film pattern (3') as a mask, the method comprises etching the thin film (2) using the lower organic resin film pattern (5') and the intermediate organic resin film pattern (5'). In the process of dry etching the lower layer organic resin film (3) using the layer metal resin film pattern (4') as a mask, the upper layer organic resin film pattern (5') is etched away and the middle layer metal resin film pattern (4') is etched away. ') The thickness of the upper organic resin film (5) is set so that the remaining thickness of the lower organic resin film (3) does not exceed 1 μm when the surface of the semiconductor device is exposed. Production method.
(2)薄膜(2)の形成された基板(1)上に下層有機
樹脂膜(3)、中間層金属樹脂膜(4)、上層有機樹脂
膜(5)を順次形成し、ついでフォトリソグラフィによ
り上層有機樹脂膜パターン(5′)を形成し、ついで該
上層有機樹脂膜パターン(5′)をマスクとしてドライ
エッチングを行い中間層金属樹脂膜パターン(4′)を
形成した後、該上層有機樹脂膜パターン(5′)及び該
中間層金属樹脂膜パターン(4′)をマスクとして磁界
を印加した反応性イオンエッチングを行い下層有機樹脂
膜パターン(3′)を形成するか、あるいは、該上層有
機樹脂膜パターン(5′)及び該中間層金属樹脂膜パタ
ーン(4′)をマスクとしてドライエッチングを行うこ
とによって該上層有機樹脂膜パターン(5′)がエッチ
ング除去され該中間層金属樹脂膜パターン(4′)の表
面が露出した後に、磁界を印加した反応性イオンエッチ
ングを行い下層有機樹脂膜パターン(3′)を形成し、
該下層有機樹脂膜パターン(3′)をマスクとして該薄
膜(2)をエッチングする工程を有することを特徴とす
る半導体装置の製造方法。
(2) A lower organic resin film (3), an intermediate metal resin film (4), and an upper organic resin film (5) are sequentially formed on the substrate (1) on which the thin film (2) has been formed, and then by photolithography. An upper layer organic resin film pattern (5') is formed, and then dry etching is performed using the upper layer organic resin film pattern (5') as a mask to form an intermediate layer metal resin film pattern (4'). A lower organic resin film pattern (3') is formed by reactive ion etching using the film pattern (5') and the intermediate metal resin film pattern (4') as a mask and applying a magnetic field, or the upper organic resin film pattern (3') is By performing dry etching using the resin film pattern (5') and the intermediate layer metal resin film pattern (4') as a mask, the upper layer organic resin film pattern (5') is etched away and the intermediate layer metal resin film pattern (4') is etched away. After the surface of 4′) is exposed, reactive ion etching is performed while applying a magnetic field to form a lower organic resin film pattern (3′),
A method for manufacturing a semiconductor device, comprising the step of etching the thin film (2) using the lower organic resin film pattern (3') as a mask.
JP1203006A 1989-08-04 1989-08-04 Manufacture of semiconductor device Pending JPH0366119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1203006A JPH0366119A (en) 1989-08-04 1989-08-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1203006A JPH0366119A (en) 1989-08-04 1989-08-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0366119A true JPH0366119A (en) 1991-03-20

Family

ID=16466773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1203006A Pending JPH0366119A (en) 1989-08-04 1989-08-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0366119A (en)

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