JPH0366181A - Light-emitting diode - Google Patents
Light-emitting diodeInfo
- Publication number
- JPH0366181A JPH0366181A JP1203161A JP20316189A JPH0366181A JP H0366181 A JPH0366181 A JP H0366181A JP 1203161 A JP1203161 A JP 1203161A JP 20316189 A JP20316189 A JP 20316189A JP H0366181 A JPH0366181 A JP H0366181A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- etching
- conductivity type
- stopper
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発!1は光通信等に用いられる面発光ダイオードの
中で、8A8構造を用いた発光ダイオードの製造方法に
関するものである。[Detailed description of the invention] [Industrial application field] This is the start! No. 1 relates to a method of manufacturing a light emitting diode using an 8A8 structure among surface light emitting diodes used for optical communications and the like.
第2図は従来の、発光ダイオードの製造工程の流れ金示
す断面図である。FIG. 2 is a cross-sectional view showing the flow of the conventional manufacturing process of a light emitting diode.
図にかいて、14iN形GaA3基板、2はN形AJ?
GaA3第1クラッド層、8はP形AlGaAS活性層
、番はP形A/GaAs第2クラッド層、5はN形A/
GaAs電流阻止層、6は堀り込みエツチングにより形
成された段差部、7はP形A/GaA9キャップ層であ
る。In the figure, 14iN type GaA3 substrate, 2 is N type AJ?
GaA3 first cladding layer, 8 P-type AlGaAS active layer, number P-type A/GaAs second cladding layer, 5 N-type A/
A GaAs current blocking layer, 6 a stepped portion formed by deep etching, and 7 a P-type A/GaA9 cap layer.
次に製造工程について説明する。壕ず、 GaA4基板
lの上に第1クラツド層8.活性層8.第2クラツド層
4.電流阻止層5を液相エピタキシャル成長法を用いて
順次形成し、(&1図に示す様なエビウェハを得る。Next, the manufacturing process will be explained. A first cladding layer 8. is formed on the GaA4 substrate 1 without trenches. Active layer 8. Second cladding layer4. A current blocking layer 5 is sequentially formed using a liquid phase epitaxial growth method to obtain a shrimp wafer as shown in FIG.
次に、写真製版、ウェットエッチ技術を用いてウェハの
一部を選択エツチングする((b1図)。Next, a part of the wafer is selectively etched using photolithography and wet etching techniques ((Figure b1)).
その後、 MootTD f!i、長法を用いてキャッ
プ層7を戊長しく0)図の様なSAS構造構造酸形成。After that, MootTD f! i. Extend the cap layer 7 using the length method to form the SAS structure as shown in the figure.
な釦エッチング工程に←いては電流阻止層5を完全にエ
ツチング除去し、電流注入領域を形成している。In the button etching process, the current blocking layer 5 is completely etched away to form a current injection region.
従来の発光ダイオードは以上のように構成されていたの
で、堀り込みエツチングの深さをエツチング液のm成、
温度、釦よびエツチング時間によシ制御しているが、ウ
ェットエッチの制御性は±20%程度であう、堀り込み
深さのばらつきによる特性のばらつきが問題点となって
いた。Conventional light emitting diodes were constructed as described above, so the depth of the digging etching was determined by the composition of the etching solution,
Although it is controlled by temperature, button and etching time, the controllability of wet etching is about ±20%, and variations in properties due to variations in digging depth have been a problem.
この発明は上記の様な問題点を解消するためになされた
もので、堀り込み深さのばらつきを少なくすることによ
って特性を安定させた発光ダイオードを得ることを目的
とする。This invention was made to solve the above-mentioned problems, and aims to provide a light emitting diode with stable characteristics by reducing variations in digging depth.
この発明に係る発光ダイオードは第2クラッド層と電流
阻止層の間にエラチン・ゲストツバ−層を設け、掘り込
み工程にかいて選択性エッチャントを用いたものである
。The light emitting diode according to the present invention has an eratin guest layer formed between the second cladding layer and the current blocking layer, and uses a selective etchant in the digging process.
この発明に釦ける電流阻止層5よびエツチングストッパ
ー層は、両層のみ金順次選択的にエツチングすることに
より、掘り込み深さのばらつきを少なくする。In the current blocking layer 5 and the etching stopper layer according to the present invention, variations in digging depth are reduced by sequentially and selectively etching only both layers with gold.
以下、この発明の一実施例金回について説明する。第1
図はこの発明の一実施間によるSAS構造の発光ダイオ
ードの製造工程の流れ金示す断面図であり、図にかいて
lばN形GaA3基板2はN形A/l’GaAa第1ク
ラッド層、8はP形A/GaAs活性層、4はP形A/
GaA4第2クラッド層、5はN形A/GaAg’[流
阻止層、6は掘り込みエツチングにより形成された一段
差部、7はP形AlGaA3キャップ層、8t/i工ツ
チングストツパー層である。Hereinafter, an embodiment of the present invention will be described. 1st
The figure is a cross-sectional view showing the flow of the manufacturing process of a light emitting diode with an SAS structure according to one embodiment of the present invention. 8 is P type A/GaAs active layer, 4 is P type A/
GaA4 second cladding layer, 5 is N-type A/GaAg' [flow blocking layer, 6 is a step portion formed by digging etching, 7 is P-type AlGaA3 cap layer, 8t/i etching stopper layer. be.
次に製造工程について説明する。1ず、GaA3基板1
の上に前記従来のものと同様Vcfi相エピタキシャル
戚長法を用りて、第1クラッド層、活性層、第2クラッ
ド層、エツチングストッパを
一層、電流阻止層を順次形成し、fJL1図に示す様な
エピウェハを得る。Next, the manufacturing process will be explained. 1. GaA3 substrate 1
A first cladding layer, an active layer, a second cladding layer, an etching stopper, and a current blocking layer are sequentially formed thereon using the Vcfi phase epitaxial growth method as in the conventional method, as shown in the fJL1 diagram. Obtain epiwafers.
次に、写真製版、ウェットエッチ技術を用いて、一部の
電流阻止層5のみ金選択エツチングする((b1図)。Next, only a part of the current blocking layer 5 is selectively etched with gold using photolithography and wet etching techniques ((Figure b1)).
電流阻止層5のA/組戊比ヲ0.8以上、ストッパー層
のAt@ffl比を0.2以下とし、弗酸系のエッチャ
ントを用いてエツチングを行うことにより、選択エツチ
ングが可能である。Selective etching is possible by setting the A/composition ratio of the current blocking layer 5 to 0.8 or more and the At@ffl ratio of the stopper layer to 0.2 or less, and performing etching using a hydrofluoric acid-based etchant. .
さらにストッパー層8をエツチングするため、アンモニ
ア−過酸化水素系のエラチャントラ用い選択エツチング
を行う((0)図)。Furthermore, in order to etch the stopper layer 8, selective etching is performed using an ammonia-hydrogen peroxide based elaschanter (FIG. (0)).
その後、MOOUD li長法を用いてキャップ層7を
戚長し1句図に示す様なSAS構造を形成する。Thereafter, the cap layer 7 is lengthened using the MOOUD li length method to form a SAS structure as shown in the first diagram.
以上のようにこの発明によれば、エツチングストッパー
層を新らたに設は選択性エッチャントを用いることによ
り、堀り込み深さのばらつきを±5%以下にすることが
でき特性が安定するという効果がある。As described above, according to the present invention, by newly forming the etching stopper layer and using a selective etchant, the variation in the digging depth can be reduced to ±5% or less, and the characteristics can be stabilized. effective.
第1図はこの発明の一実施的による発光ダイオードの製
造工程、を示す断面図、第2図は従来の発光ダイオード
の製造工程を示す断面図である。
区VCかいて、lけGaAB基板、2は第1クラツド眉
、81d活性層、4は第2クラッド層、5は電流阻止層
、6Vi堀り込みにより段差部、7はキャップ層、8I
riエツチングストッパー層金示す。
なか、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a sectional view showing the manufacturing process of a light emitting diode according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the manufacturing process of a conventional light emitting diode. VC is drawn, 1 is the GaAB substrate, 2 is the first cladding layer, 81d is the active layer, 4 is the second cladding layer, 5 is the current blocking layer, 6 is the stepped portion by digging, 7 is the cap layer, 8I
The RI etching stopper layer metal is shown. In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
形の半導体基板上に第1導電形の第1クラッド層、第2
導電形の活性層、第2導電形の第2クラッド層、第2導
電形のストッパー層、第1導電形の電流阻止層を順次形
成し、前記第1導電形の電流阻止層の一部を選択性エッ
チャントを用いてエッチング除去した後、前記第2導電
形のストッパー層の一部を選択性の異なるエッチャント
を用いてエッチング除去し、さらに、その上に第2導電
形のキャップ層を形成したことを特徴とする発光ダイオ
ード。In an AlGaAS-based SAS structure LED, a first cladding layer of a first conductivity type, a second cladding layer of a first conductivity type are formed on a semiconductor substrate of a first conductivity type.
An active layer of a conductivity type, a second cladding layer of a second conductivity type, a stopper layer of a second conductivity type, and a current blocking layer of a first conductivity type are sequentially formed, and a part of the current blocking layer of the first conductivity type is formed. After removing it by etching using a selective etchant, a part of the stopper layer of the second conductivity type was removed by etching using an etchant with different selectivity, and further, a cap layer of the second conductivity type was formed thereon. A light emitting diode characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1203161A JPH0366181A (en) | 1989-08-04 | 1989-08-04 | Light-emitting diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1203161A JPH0366181A (en) | 1989-08-04 | 1989-08-04 | Light-emitting diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0366181A true JPH0366181A (en) | 1991-03-20 |
Family
ID=16469451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1203161A Pending JPH0366181A (en) | 1989-08-04 | 1989-08-04 | Light-emitting diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0366181A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0556863A3 (en) * | 1992-02-20 | 1994-01-19 | Sumitomo Electric Industries | |
| JPH06151959A (en) * | 1992-11-06 | 1994-05-31 | Shin Etsu Handotai Co Ltd | Method for manufacturing GaAlAs light emitting device |
| US7927901B2 (en) | 2008-07-18 | 2011-04-19 | Lextar Electronics Corp. | Method for fabricating LED chip comprising reduced mask count and lift-off processing |
-
1989
- 1989-08-04 JP JP1203161A patent/JPH0366181A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0556863A3 (en) * | 1992-02-20 | 1994-01-19 | Sumitomo Electric Industries | |
| US5359619A (en) * | 1992-02-20 | 1994-10-25 | Sumitomo Electric Industries, Ltd. | Multi-beam semiconductor laser and method for producing the same |
| JPH06151959A (en) * | 1992-11-06 | 1994-05-31 | Shin Etsu Handotai Co Ltd | Method for manufacturing GaAlAs light emitting device |
| US7927901B2 (en) | 2008-07-18 | 2011-04-19 | Lextar Electronics Corp. | Method for fabricating LED chip comprising reduced mask count and lift-off processing |
| US8173467B2 (en) | 2008-07-18 | 2012-05-08 | Lextar Electronics Corp. | Method for fabricating LED chip comprising reduced mask count and lift-off processing |
| US8173468B2 (en) | 2008-07-18 | 2012-05-08 | Lextar Electronics Corp. | Method for fabricating LED chip comprising reduced mask count and lift-off processing |
| US8173465B2 (en) | 2008-07-18 | 2012-05-08 | Lextar Electronics Corp. | Method for fabricating LED chip comprising reduced mask count and lift-off processing |
| US8173466B2 (en) | 2008-07-18 | 2012-05-08 | Lextar Electronics Corp. | Method for fabricating LED chip comprising reduced mask count and lift-off processing |
| US8178376B2 (en) | 2008-07-18 | 2012-05-15 | Lextar Electronics Corp. | Method for fabricating LED chip comprising reduced mask count and lift-off processing |
| US8178377B2 (en) | 2008-07-18 | 2012-05-15 | Lextar Electronics Corp. | Method for fabricating lED chip comprising reduced mask count |
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