JPH036650A - Bidirectional data bus circuit - Google Patents

Abstract

PURPOSE:To transfer data at a high speed and in a short time by transferring the data simultaneously in both directions. CONSTITUTION:An output signal line 10 of a 1st driver 1 and an input signal line 13 of a 1st receiver 3 are connected to one of both ends of a data bus line 5. At the same time, an output signal line 11 of a 2nd driver and an input signal line 15 of a 2nd receiver 4 are connected to the other end of the line 5. Furthermore the control input signal lines 12 and 14 of both receivers 3 and 4 are connected to the input signal lines 6 and 7 of both drivers 1 and 2 respectively. Then the data are transferred to the receiver 4 from the driver 1 via the line 5. At the same time, the data are transferred to the receiver 3 from the driver 2. Thus the data can be transferred at a high speed and in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bidirectional data bus circuit for a microprocessor system used in, for example, a facsimile machine.

[Prior Art] Conventionally, typical data buses in microprocessor systems include an address data bus and a memory read/write bus that connect a microprocessor and an external memory. In the address data bus, address data is transferred unidirectionally rather than bidirectionally. on the other hand,
In the memory read/write data bus, data is transferred bidirectionally, but a method is adopted in which the data is separated into two types of cycles, a read cycle and a write cycle, and the data transfer direction is changed in a time-division manner.

[Problems to be Solved by the Invention] In the conventional address data bus described above, when data is transferred by changing the transfer direction, the time axis is separated and data is transferred in each direction, so the data transfer takes a long time. 3 [Means for Solving the Problem] FIG. 1 is a block diagram showing the basic concept of a bidirectional data bus circuit of the present invention. In FIG. 1, reference numeral 1.2 denotes first and second cable drivers (hereinafter referred to as drivers) that send signals to the data bus line 5. 3.4 receives the signal from the data bus line 5. This is a second cable receiver (hereinafter referred to as receiver). The data bus line 5 is connected to the first. Second. A third different potential level is taken. 6 and 7 are input signal lines to the driver 1.degree. 2, and 8 and 9 are output signal lines from the receivers 3 and 4. 10.11 is the output signal line of driver 1゜2, 12.
14 is a control input signal line for receiver 3.4, 13.15
are input signal lines of receivers 3 and 4.

In the bidirectional data bus circuit of the present invention, the output signal line 10 of the first driver 1 is connected to one end of the data bus line 5.
and the input signal line 13 of the first receiver 3, and the output signal line 11 of the second driver 2 and the input signal line 15 of the second receiver 4 are connected to the other end of the data bus line 5.
1st. The first input signal line 6.7 of the second driver 1.2
．． Control input signal lines 12.14 for second receivers 3 and 4
are connected to each other. And data bus line 5
Data is transferred from the first driver 1 to the second receiver 4 via the first driver 1, and data is also transferred from the second driver 2 to the first receiver 3 via the first driver 1.

[Effect] 1st. The second drivers 1 and 2 have an input logic of “0”.
”, set the data bus line 5 to the first potential,
If one input logic is "0" and the other input logic is "
If the input logic is "1", the data bus line 5 is set to the second potential, and if both input logics are "1", the data bus line 5 is set to the third potential. 1st. The second receivers 3, 4 have a logic "?" when the data bus line 5 is at the first potential.
When the data bus line 5 is at the second potential and the control input signal line 12.14 is at the logic "0", it outputs the logic "1", and the data bus line is at the second potential. At the same time, the control input signal lines 12 and 14 are logic "
1", the logic "0" is output, and when the data bus line is at the third potential, the logic "r1. Output.

Therefore, the first. When a logic "0" is applied to both input signal lines 6.7 of the second driver 1.2, the data bus line 5 is set to the first potential, so that the first. Logic "0" is output to the output signal lines of the second receivers 3 and 4. Also, 1st. Input signal line 6 of second driver 1, 2
, 7 is given logic "0" and the other is given logic "1", the data bus line 5 is set to the second potential, so that the control input signal line 12 or 1
Receiver 3 or 4 given logic “0” via 4
A logic "1" is output to the output signal line 11 or 13 of the circuit. Also, 1st. Input signal line 6 of second driver 1, 2
．． When logic "1" is applied to both of the first and second lines, the data bus line 5 is set to the third potential. A logic "1" is output to the output signal lines 8, 9 of the second receiver 3.4.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 2 is a configuration diagram showing one embodiment of the present invention, and the first
The same reference numerals as those in the drawings indicate corresponding parts, and the explanation thereof will be omitted.

In the driver 1, 1a is a transistor that drives the data bus 5, 1b is a transistor drive buffer that drives the transistor 1a, and IC is a voltage dividing resistor whose one end is connected to the voltage Ec and the other end is connected to the collector of the transistor 1a. . The driver 2 also has a similar configuration.

The data bus router is grounded via a voltage dividing resistor 5a.

Further, the resistance values R of the voltage dividing resistors 1c, 2c, and 5a are all the same.

In the receiver 3, 3a indicates three potential levels El, E2 . A voltage level identification circuit (hereinafter referred to as an identification circuit) which inputs E3 as an input potential ■ via the input signal line 13 and outputs signals rQ, rl, as output logics LL, L2 corresponding to these three voltage levels. 3b inputs the logic level of the input signal line 6 via the control input line 12, and also inputs the output logic level from the output terminals LL and L2 of the identification circuit 3a.
This is a voltage level determination circuit (hereinafter referred to as determination circuit) that outputs the logic level of LJ, and is composed of an AND circuit 3c and an OR circuit 3d.The receiver 4 also has a similar configuration.

Next, the operation will be explained.

The drivers 1 and 2 are configured to set the potential of the data bus line 5 via the output signal line 10.11 according to the input logics A and B of the input signal line 6.7, as shown below.

■Input logic A and B of both input signal lines 6 and 7 are “
0'', the transistor drive buffers 1b and 2b turn off the transistors la and 2a, so the data bus line 5 becomes approximately at ground potential. That is, the potential E1 at this time becomes E1-O.

■When the input logic A or B of one of the input signal lines 6 and 7 is "1" and the other is "0", the transistor l
Since either a or 2a is on and the other is off, the potential E2 of the data bus line 5 at this time is divided by the voltage dividing resistors 1c, 5a or 2c, 5a, and E2#Ec -R/ ( 2R)=Ec/2.

■Input logic A and B of both input signal lines 6 and 7 are “
1, both transistors la and 2a are on, so the potential E3 of the data bus line 5 at this time is divided by the voltage dividing resistors 1c, 2c, and 5a, and becomes E3#Ec -R/ (1, 5R)=2Ec/3.

As explained above, the potentials of the data bussler are El, E
2. It is set to three different potential levels of E3.

On the other hand, the receiver 3 sets the output logic C of the output signal line 8 according to the inputs from the control input signal line 12 and the input signal line 13. The output logic of the output signal line 9 is set according to the input from the input signal line 15.

Table 1 is an input/output logic table for receiver 3. However, in Table 1, ■ is the potential of the data bus 5, that is, the input potential of the identification circuit 3a, Ll and L2 are the output logic of the identification circuit 3a, and A is the control input signal line 12.
．． That is, C is the input logic of the determination circuit 3b, and C is the output logic of the receiver 3, that is, the output logic of the determination circuit 3b. The operation of the receiver 3 will be described below with reference to Table 1.

Table 1 ■ When the potential of the data bus etc. is potential E1 and the input logic of the control input signal line 12 is "O", the receiver 3 is at the logic "0".
" is output.

■When the potential of the data bus router is the potential E2 and the input logic of the control input signal line 12 is "1", the receiver 3 has the logic rQ
Output J.

■When the potential of the data bus router is the potential E2 and the input logic of the control input signal line 12 is "0", the receiver 3 has the logic "1".
" is output.

(2) When the potential of the data bus 5 is the potential E3, the receiver 3 outputs logic "1".

Note that the input/output logic of the receiver 4 is also the same as above.

Next, the output signal lines 8 of the receivers 3 and 4 are
．． The operation in which output logics C and D are set in 9 will be explained with reference to Table 2.

Table 2 (1) When “0” is given to both input signal lines 6 and 7 of driver 1.2 Since both driver 1.2 is given logic “0”,
Data bus line 5 is set to potential E1. As a result, input signal lines 13.15 of receivers 3 and 4 are set to potential E1, so receivers 3.4 output logic "0" to output signal lines 8.9, respectively.

That is, in this case, logical "0" data is transferred in both directions at the same time.

(2) If logic "0" is given to input signal line 6 of driver 1 and logic "IJ" is given to input signal line 7 of driver 2, logic "0" is given to one of drivers 1 and 2, and logic "0" is given to the other. Since "1" is applied, data bus line 5 is set to potential E2. As a result, the input signal lines 13.15 of the receivers 3 and 4 are set to the potential E2. At the same time, the control input signal line 12 of the receiver 3 has a logic “0”.
” is set, the receiver 3 sets the output signal line 8 to logic “1”. On the other hand, since the control input signal line 14 of the receiver 4 is set to logic "1", the receiver 4 outputs the logic "0" to the output signal line 9.

That is, in this case, data of logical "0" and "1" is transferred simultaneously in both directions.

In addition, contrary to the above, if logic "1" is given to driver 1 and logic "0" is given to driver 2, "
An operation is performed in which ``0'' and ``1'' are reversed.

G) When logic "1" is given to both input signal lines 6 and 7 of drivers 1 and 2 Since both drivers 1 and 2 are given logic "1",
Data bus line 5 is set to potential E3. As a result, input signal lines 13.15 of receivers 3 and 4 are set to potential E3, so receivers 3.4 output logic "1" to output signal lines 8 and 9, respectively.

That is, in this case, data of logic "1" is transferred in both directions at the same time.

In addition, in this embodiment, as shown in FIG.
c, 2c, 5a have the same resistance value R, the potential level of data bus line 5 E1, E2 . E3 to O,
Although Ec/2 and 2Ec/3 are used, the potential level is not limited to this, and the potential level can be changed by setting the voltage dividing resistor to a different value.

[Effects of the Invention] As explained above, according to the bidirectional data transfer circuit of the present invention, when logic "0" is applied to both the input signal lines of the first and second drivers, the data bus line 1
Therefore, logic "0" is output to the output signal lines of the first and second receivers. Furthermore, if logic "0" is given to one of the input signal lines of the first and second drivers, and logic "1" is given to the other,
Since the data bus line is set to the second potential, a logic "1" is output to the output signal line of the receiver to which a logic "0" is applied via the control input signal line. Also, the first
and logic “1” on both input signal lines of the second driver.
is applied, the data bus line is set to the third potential, so a logic "1" is output to the output signal lines of the first and second receivers. Therefore, by performing the data transfer operation in this way, unlike conventional data buses, bidirectional data transfer can be performed at the same time. It has the advantage of being able to transfer data in minutes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic concept of the invention, and FIG. 2 is a block diagram showing an embodiment of the invention. 1.2...driver, 3,4...receiver, 5...
・Data bus line, 6,7.13.15...-Human signal line, 8,9,10.11...Output signal line, 12゜1
4...Control input signal line.

Claims (1)

[Claims] The output signal line of the first cable driver and the input signal line of the first cable receiver are connected to one end of the data bus line, and the output signal line of the second cable driver is connected to the other end of the data bus line. The signal line and the input signal line of the second cable receiver are connected, and the control input signal lines of the first and second cable receivers are connected to the input signal lines of the first and second cable drivers, respectively. A bidirectional data bus circuit for transferring data from a first cable driver to a second cable receiver via a bus line, and for transferring data from the second cable driver to the first cable receiver, the circuit comprising: and the second cable driver sets the data bus line to the first potential when both input logics are "0", and one of the input logics is "0" and the other input logic is "1". The first and second cable receivers set the data bus line to a second potential when the data bus line When the data bus line is at the first potential, a logic "0" is output, and when the data bus line is at the second potential and the control input signal line is a logic "0", a logic "1" is output, and the data Outputs logic "0" when the bus line is at the second potential and the control input signal line is at logic "1", and outputs logic "1" when the data bus line is at the third potential A bidirectional data bus circuit characterized by: