JPH1031647A - Cpu board having data bus width conversion control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the DMA data transfer between a 16-bit device and a 32-bit device by outputting the control signals to a data bus width conversion buffer and a memory via a data bus width conversion control circuit when the device built into a 16-bit DMA controller is used as a bus master. SOLUTION: When a device 4 with built-in 16-bit DMA controller is used as a bus master, a data bus width conversion control circuit 5 inputs the least significant bit of the address signal put on an address bus 12 and outputs a control signal to a data but width conversion buffer 3 to instruct the connection between higher 16 bits of a 32-bit data bus 11 and a 16-bit data bus 13 when the value of the least significant bit is equal to 0. Then the circuit 5 outputs a control signal to 32-bit memory 2 to show that the higher 16 bits are valid. Thus, the DMA data transfer can be performed between the device 4 and the memory 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU board, and more particularly to a CPU having a built-in device for a direct memory access (hereinafter, referred to as DMA) controller having a data bus width different from that of a CPU and a memory.
About the board.

[0002]

2. Description of the Related Art As an example of DMA control of a device having a data bus width different from that of a data bus of a CPU and a memory in the prior art, an invention of a direct memory access controller described in Japanese Patent Application Laid-Open No. Hei 5-94404 is disclosed. There is.

FIG. 2 is a block diagram showing a configuration of a CPU board in a conventional example, and shows a configuration of the invention described in the above publication.

[0004] The CPU board shown in FIG.
CPU with a data bus width of
U) 1 and a memory having a data bus width of 32 bits (hereinafter referred to as a 32-bit memory)
2, a DMA controller 6, a device 7 having a data bus width of 16 bits (hereinafter referred to as a 16-bit device) 7, a 32-bit data bus 21, and 16 bi.
t data bus 23.

[0005] The 32-bit CPU 1 is connected to a 32-bit data bus 21. 32 bit memory 2 is 3
It is connected to a 2-bit data bus 21. The DMA controller 6 has the 32-bit data buses 21 and 16b
It is connected to the data bus 23. The 16-bit device 7 is connected to a 16-bit data bus 23.

In FIG. 2, a 16-bit device 7 is connected to a 32-bit CPU 1 via a DMA controller 6.
And a 32-bit memory 2 to transfer data between the 16-bit device 7 and the 32-bit memory 2 by DMA transfer.

When performing a DMA transfer, a signal requesting the DMA transfer is output from the 16-bit device 7 to the DMA controller 6.

When data is transferred from the 16-bit device 7 to the 32-bit memory 2, the DMA controller 6 first outputs a read signal to the 16-bit device 7 to read data. Since the data read from the 16-bit device 7 is 16 bits, the data is stored in a buffer built in the DMA controller 6 at the time of the first reading. Similarly, the second reading is performed, and at the time of the second reading, the DMA controller 6
Writes 32-bit data to the 32-bit memory 2 together with the previously read data.

When transferring data from the 32-bit memory 2 to the 16-bit device 7, the DMA controller 6 reads out 32-bit data from the 32-bit memory 2 and writes the data into the 16-bit device 7 in two separate operations.

[0010]

A problem of the prior art is that it cannot be applied to a case where a device having a built-in DMA controller and having a data bus width different from that of a memory data bus is connected. Therefore, when connecting a device having a different data bus width from the data bus of the memory with a built-in DMA controller, the data bus connected to the device must be connected to the upper 16 bits or the lower 16 bits of the memory and used. Alternatively, in addition to the DMA controller built in the device, it is necessary to mount a DMA controller as described in the related art on the CPU board, which causes a problem of increasing the cost of the CPU board.

The reason is that in the prior art, data can be stored in a buffer built in a DMA controller external to the device to access memories having different data bus widths. This DMA controller has the same width as the memory. Must be connected to the data bus. On the other hand, in a device having a built-in DMA controller and a data bus width different from that of a memory, the built-in DMA controller can be connected only to a data bus having a bus width different from that of the memory similarly to the device.

An object of the present invention is to provide a device having a built-in DMA controller and having a data bus width of 16 bits.
DMA between memory having a data bus width of 2 bits
Is to enable data transfer.

[0013]

In order to solve the above problems, a CPU board having a data bus width conversion control circuit according to the present invention comprises a CPU having a data bus width of 32 bits and a data bus width of 32 bits. A built-in device with a direct memory access controller having a 16-bit data bus width capable of acting as a bus master and accessing the memory by direct memory access transfer;
A data bus width conversion buffer and a data bus width conversion control circuit, wherein the CPU is connected to a 32-bit data bus and an address bus, and the memory is connected to the 32-bit data bus and the address bus; If the device with the built-in memory access controller is 16b
It is connected to the data bus and the address bus, the data bus width conversion buffer is connected to the 32-bit data bus and the 16-bit data bus, and the data bus width conversion control circuit is connected to the address bus.

In the CPU board having the data bus width conversion control circuit according to the present invention, when the data bus width conversion control circuit is configured such that the device with a built-in direct memory access controller becomes a bus master, the data bus width conversion buffer and the data bus width conversion buffer Outputs control signals to the memory.

In the present invention having such a configuration, the data bus width conversion buffer outputs the data bus width conversion buffer from the device with the built-in DMA controller having the data bus width of 16 bits to the 16-bit data bus according to the control signal output from the data bus width conversion control circuit. Enter the transferred data and enter 32bi
It is possible to output to either the upper 16 bits or the lower 16 bits specified by the address signal of the t data bus. Therefore, the data output from the built-in DMA controller of the device with a built-in DMA controller having a data bus width of 16 bits to the 16-bit data bus is transferred to the upper 16 bits of the 32-bit data bus.
It becomes possible to input it or the lower 16 bits.

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

[1] Description of Configuration FIG. 1 is a block diagram showing a configuration of a CPU board according to an embodiment of the present invention.

The configuration of an embodiment of the present invention will be described in detail with reference to FIG.

As shown in FIG. 1, a preferred embodiment of the present invention comprises a CPU (hereinafter referred to as a 32-bit CPU) 1 having a 32-bit data bus width, and a 32-bit CPU.
memory with a data bus width of 32 bit (hereinafter, 32 bits)
2) and a data bus width conversion buffer 3
A device having a built-in DMA controller having a data bus width of 16 bits (hereinafter referred to as a device having a built-in 16-bit DMA controller) 4, a data bus width conversion control circuit 5, a 32-bit data bus 11, an address bus 12, and a 16-bit device. It has a data bus 13.

The 32-bit CPU 1 is connected to a 32-bit data bus 11 and an address bus 12. 3
The 2-bit memory 2 is connected to a 32-bit data bus 11 and an address bus 12. The data bus width conversion buffer 3 includes a 32-bit data bus 11 and a 16-bit data bus.
It is connected to both the data bus 13. 16 bits
The device 4 with a built-in DMA controller
It is connected to a 2 and 16 bit data bus 13.
The data bus width conversion control circuit 5 outputs a control signal to the data bus width conversion buffer 3 and the 32-bit memory 2.

[2] Description of Operation The operation of the embodiment of the present invention will be described in detail with reference to FIG.

A case where data is transferred from the 32-bit memory 2 to the device 4 with a 16-bit DMA controller by DMA transfer will be described. In this case, 1
The device 4 with a built-in 6-bit DMA controller acts as a bus master and outputs an address signal indicating the address of the transfer data on the address bus 12.

The data bus width conversion control circuit 5 inputs the least significant bit of the address signal on the address bus 12 and
When the value is 0, a control signal for instructing connection of the upper 16 bits of the 32-bit data bus 11 and the 16-bit data bus 13 is transmitted to the data bus width conversion buffer 3.
And a control signal indicating that the upper 16 bits are valid is output to the 32-bit memory 2. When the least significant bit of the address signal on the address bus 12 is input and the value is 1, the data bus width conversion control circuit 5 sets the lower 16 bits of the 32-bit data bus 11 to 1
A control signal for instructing connection to the 6-bit data bus 13 is output to the data bus width conversion buffer 3 and the lower 16
The control signal indicating that the bit is valid is 32 bi
Output to the t memory 2.

The 32-bit memory 2 has an address bus 12
Only the upper 16 bits or lower 16 bits of data indicated to be valid by the control signal output from the data bus width conversion control circuit 5 corresponding to the least significant bit of the address signal input from the
Output to the data bus 11.

The data bus width conversion buffer 3 operates according to a control signal output from the data bus width conversion control circuit 5.
Either the upper 16 bits or the lower 16 bits of the 32-bit data bus 11 is output onto the 16-bit data bus 13.

The 16-bit DMA controller built-in device 4 inputs data on the 16-bit data bus 13 as read data from the 32-bit memory 2 in accordance with the designated address. By this, 32 bits
DMA data transfer from the memory 2 to the 16-bit DMA controller built-in device 4 is executed.

Next, a 16-bit DM is transferred by DMA transfer.
32-bit memory 2 from device 4 with built-in A controller
Will be described. Also in this case, similarly to the above case, the device 4 with a built-in 16-bit DMA controller becomes a bus master and outputs an address signal indicating the address of the transfer data onto the address bus 12.

The data bus width conversion control circuit 5 inputs the least significant bit of the address signal on the address bus 12 and
When the value is 0, a control signal for instructing connection of the upper 16 bits of the 32-bit data bus 11 and the 16-bit data bus 13 is transmitted to the data bus width conversion buffer 3.
And a control signal indicating that the upper 16 bits are valid is output to the 32-bit memory 2. When the least significant bit of the address signal on the address bus 12 is input and the value is 1, the data bus width conversion control circuit 5 sets the lower 16 bits of the 32-bit data bus 11 to 1
A control signal for instructing connection to the 6-bit data bus 13 is output to the data bus width conversion buffer 3 and the lower 16
The control signal indicating that the bit is valid is 32 bi
Output to the t memory 2.

The 16-bit DMA controller built-in device 4 outputs the transfer data to the 16-bit data bus 13.

The data bus width conversion buffer 3 operates in accordance with a control signal output from the data bus width conversion control circuit 5.
The data on the 16-bit data bus 13 is output to either the upper 16 bits or the lower 16 bits of the 32-bit data bus 11.

The 32-bit memory 2 stores 32 bits according to a control signal output from the data bus width conversion control circuit 5.
upper 16 bits or lower 16b on the t data bus 11
Only one of the data of “it” is input and stored. Thus, DMA data transfer from the 16-bit DMA controller built-in device 4 to the 32-bit memory 2 is performed.

[0032]

As described above, according to the present invention, the control signal output from the data bus width conversion control circuit causes the data bus width conversion buffer to shift from the device with the built-in DMA controller having a data bus width of 16 bits to 16 bi.
t The transfer data output to the data bus is input and 32
The data can be output to either the upper 16 bits or the lower 16 bits specified by the address signal in the bit data bus. Therefore, the data output from the built-in DMA controller of the device with a built-in DMA controller having a data bus width of 16 bits to the 16-bit data bus is transferred to the upper 16 bits of the 32-bit data bus.
It can be input to it or lower 16 bits.

In this manner, data can be transferred by DMA between a device having a built-in DMA controller having a data bus width of 16 bits and a device having a data bus width of 16 bits and a memory having a data bus width of 32 bits. Have. As a result, 16 bits
A device with a built-in DMA controller with a data bus width of half the memory capacity required for performing data transfer by DMA can be halved, and the same functions as before can be realized, resulting in a low-cost CPU board. It has the effect that it can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a CPU board according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a CPU board in a conventional example.

[Explanation of symbols]

 1 32-bit CPU 2 32-bit memory 3 Data bus width conversion buffer 4 16-bit device with built-in DMA controller 5 Data bus width conversion control circuit 6 DMA controller 7 Device 11/21 32-bit data bus 12 Address bus 13, 23 16-bit data bus

Claims (2)

[Claims] 1. A CP having a data bus width of 32 bits.
A CPU board having U and a memory having a data bus width of 32 bits, a device with a built-in direct memory access controller having a data bus width of 16 bits capable of acting as a bus master and accessing the memory by direct memory access transfer; A data bus width conversion buffer,
A data bus width conversion control circuit, the CPU is connected to a 32-bit data bus and an address bus, the memory is connected to the 32-bit data bus and the address bus, and the device with a direct memory access controller is The data bus width conversion buffer is connected to the 16-bit data bus and the address bus, the data bus width conversion buffer is connected to the 32-bit data bus and the 16-bit data bus, and the data bus width conversion control circuit is connected to the address bus. A CPU board having a data bus width conversion control circuit. 2. The data bus width conversion control circuit outputs a control signal to the data bus width conversion buffer and the memory when the device with a built-in direct memory access controller becomes a bus master. CPU board having a data bus width conversion control circuit.