JPH0367280B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speech synthesis device for resynthesizing speech based on speech characteristic parameters extracted from speech.

[Prior art]

This type of speech synthesizer uses LSP (Line), which can obtain the same synthesized speech quality with about 60% of the amount of information compared to the conventional PARCOR method, which was the mainstream.
There is an urgent need to develop a speech synthesizer based on SPectrum Pair.

The LSP method is a further improvement of the PARCOR method, and basically, like the PARCOR method, as shown in Figure 1, the sound source generated by the human vocal cords is simulated by the sound source generator 1. The sound source signal is generated as a sound source signal in the digital film 3, which is controlled based on the frame-by-frame feature parameters of the sound stored in the parameter ROM 2, and on which the human vocal tract characteristics are modeled. A digital audio waveform signal is obtained from this filter 3, which is converted into an analog audio waveform signal by a D/A converter 4, and audio is generated from a speaker 5.

However, the LSP method differs from the PARCOR method in that it uses digital film 3 as a parameter.
Characteristic parameters representing frequencies stored in ROM2, that is, for example, eight sets of LSP frequencies ω ₁ , ω ₂ ,...
Moreover, these LSP frequencies ω ₁ , _{ω 2 ,} .
This enables extensive information compression.

As shown in Figure 2a, the parameter ROM 2 currently used in such an LSP-based speech synthesizer has a frame area of 32 bits consisting of 4 consecutive addresses (8 bits per address), upper and lower for each address. It is divided into 8 regions of 4 bits each, and each LSP frequency ω ₁ , ω ₂ , ..., is assigned to each of these 8 regions.
ω ₈ is stored.

On the other hand, if the amount of change between each value of the eight LSP frequencies to be stored in the frame area of parameter ROM2 and each value of the eight LSP frequencies stored in the previous frame area is small, is the second
As shown in Figure b, each difference value △ω ₁ , △ω ₂ , ..., △ω ₈ from the previous frame of LSP frequency is
The amount of information can be further compressed by quantizing it into bits and storing it in a 24-bit frame area consisting of three addresses in the parameter ROM 2 successively starting from the most significant bit of each address.

However, as mentioned above, each difference value △ω ₁ , △ω ₂ , ..., △ω ₈ of the LSP frequency is set to the parameter ROM2.
When storing each difference value in each frame, as is clear from Fig. 2b, unlike the case of Fig. 2a, the 3-bit difference area for storing each difference value may span consecutive addresses. , Moreover, the differential area for each address is irregular.

Therefore, a frame area in which normal LSP frequencies ω ₁ , ω ₂ , ..., ω ₈ are stored in the parameter ROM2,
If frame areas storing the difference values △ω ₁ , △ω ₂ , ..., △ω ₈ coexist, it is necessary to read out each LSP frequency or its difference value one by one according to each case. A separate reading means is required, which has the drawback of complicating the structure of this type of speech synthesis apparatus.

[Purpose of the invention]

The present invention has been made to solve the above-mentioned drawbacks, and each frame area of the parameter memory has a plurality of standard areas for storing each LSP frequency and a plurality of difference areas for storing their difference values. ,
The present invention provides an LSP-based speech synthesis device that enables the mapping of

[Structure of the invention]

The speech synthesis device of the present invention uses a frame area consisting of consecutive M addresses or m (<M) addresses of a parameter memory composed of N bits per address.
As shown in Fig. 3, it is divided vertically into M-bit or m-bit areas consisting of the n-th bit (n = 1, 2, ..., N) of each address, and these M-bit areas are divided into N areas. The first to Nth standard areas P ₁ , P ₂ ,
..., N LSPs each quantized to M bits in P _N
Frequencies ω ₁ , ω ₂ , ..., ω _N are respectively stored, while m-bit first to Nth difference regions P ₁ ', P ₂ ', ...,
The difference value △ which is quantized into each m bit in P _N
ω ₁ , △ω ₂ , ..., △ω _N are stored respectively.

〔Example〕

FIGS. 4a and 4b show parameter memories used in the speech synthesis device of the present invention, specifically parameters.
An example of partitioning a frame area of a ROM is shown.

That is, a set of 8 bits each quantized to 4 bits.
When storing the LSP frequencies ω ₁ , ω ₂ , ..., ω ₈ in a frame area, this frame area is made up of 32 bits consisting of 4 addresses of 8 bits per address, as shown in Figure 4a, and each address is The first LSP frequency ω ₁ is stored in the first standard area P ₁ of vertically divided 4-bit configuration consisting of the first bit of
Similarly, the second LSP frequency ω 2 is stored in the second standard area P ₂ of the vertically divided 4-bit configuration consisting of the second bit, and the second LSP frequency ω ₂ is similarly stored in the second standard area P ₂ consisting of the second bit. Eight LSP frequencies ω ₃ to ω ₈ are stored.

On the other hand, when storing the difference values △ω ₁ , △ω ₂ , ..., △ω _N quantized into 3 bits each of a set of 8 LSP frequencies in the frame area, the frame area is As shown in the figure, it has a 24-bit configuration consisting of 3 addresses of 8 bits per address, and is made to correspond to the 8 vertically divided standard areas P ₁ , P ₂ , ... P ₈ when directly storing the LSP frequency mentioned above. , the first difference value △ω 1 is stored in the vertically divided 3-bit first difference area P ₁ ' consisting of the first bit of each address, and the first difference value Δω ₁ is stored in the eighth difference area P ₈ ' in the same manner. Until then, the second to eighth difference values Δω ₂ to Δω ₈ are stored. still,
Each one bit located at the fourth address of each standard area P ₁ , P ₂ , ..., P ₈ corresponds to the LSP frequency ω ₁ , ω ₂ ,
_{. _ _ _} The most significant bit of ω ₁ , Δω ₂ , . . . , Δω ₈ is the sign bit.

FIG. 5 shows an embodiment of a reading means for reading out the LSP frequency or the difference value thereof from the parameter ROM 2 used in the speech synthesis apparatus of the present invention. In addition, the parameter ROM2 in the same figure is shown in Figure 4a.
The frame area F in which _the LSP frequencies ω ₁ , ω _{2 ,} ..., ω ₈ shown in FIG. There is also a frame area F′ which also stores ω ₈ vertically. In the figure, R ₁ , R ₂ , R ₃ , and R ₄ are first, second, third, and fourth registers, which are connected in parallel to the parameter ROM 2. A is a 4-bit adder, and one input value is a total of 4 bits of data output one bit each from the four registers R ₁ , R ₂ , R ₃ , and R ₄ . SW1 is the first switch, and by closing this switch SW1 to side a, the output terminal of the fourth register _R4 and the fourth bit (sign) of one input of adder A are connected. bit) and set this switch SW1 to
By closing on the side, the above third register
The output terminal of _R4 is connected to the third bit of one input of adder A as well as its fourth bit (sign bit). B ₁ , B ₂ , B ₃ , and B ₄ are first, second, third, and fourth shift registers, into which the addition output from the adder A is input shifted. SW2,... are four second switches, and the other input of the adder A is connected to ground, that is, the zero value, by closing each of these switches SW2,... to side a. , and each switch
By closing SW2, ... on the b side, it is connected to each of the above shift registers B ₁ , B ₂ , B ₃ , B ₄ and from each shift register B ₁ , B ₂ , B ₃ , B ₄ Data consisting of a total of 4 bits shifted out one bit at a time becomes the other input of adder A.

Next, the operation of such reading means will be described.

() When reading the LSP frequencies ω ₁ , ω ₂ , ..., ω ₈ for each frame area F from the parameter ROM2, in this case, close the first switch SW1 and each second switch SW2, ... to the a side. In some cases, the transmission line from the third register R ₃ to the adder A and the transmission line from the fourth register R ₄ to the adder A may be separated and the other input value of this adder A may be It is set to zero so that no addition is performed.

First, frame area F of parameter ROM2
The contents of the first to fourth addresses are sequentially written to the first to fourth registers R ₁ to R ₄ . Thereafter, these registers R ₁ to R ₄ are each shifted by 1 bit, and the 8th LSP of 4 bits stored in the 8th bit is
four shift registers B ₁ in which the frequency ω ₈ is shifted in synchronization with the registers R ₁ to R ₄ through an adder A that does not perform substantial addition;
. . . , each bit is distributed and input to _B4 .
Thus, by eight shifting operations of the registers R ₁ , . _{. . , R 4 and the} shift registers B ₁ , .
..., ω ₁ are sequentially input _{to the} shift registers _{B 1} , _.
ω ₂ ′, ..., ω ₈ ′ are rewritten to new LSP frequencies ω ₁ , ω ₂ , ..., ω ₈ in the current frame period.

() LSP frequency difference value △ω ₁ , △ω ₂ , ..., △ in frame area F′ unit from parameter ROM2
When reading out ω ₈ , in this case, the output terminal of the third register R3 and the adder A are connected by closing each of the second switches _SW2 ,... to the b side together with the first switch SW1. 3rd bit and 4th bit of one input
The other input value of this adder A is connected to the shift register B ₁ , ~,
Leave it in a state where the value is B ₄ .

First, frame area F of parameter ROM2
The contents of the first to third addresses are sequentially written to the first to third registers R ₁ , R ₂ , and R ₃ . In this case, writing to the fourth register _R4 is not performed. Then these registers
R ₁ , R ₂ , and R ₃ are each shifted by 1 bit and become one input of adder A, but at this time, what is written in the third register R ₃ is the difference value △
Since each sign bit is ω ₁ , △ω ₂ , ..., △ω ₈ , the output (sign bit) from this third register R 3 is sent to the fourth register R ₃ via switch SW 1 .
The bit is expanded to the th bit (sign bit), allowing the adder A to determine the sign. on the other hand,
The other input of the adder A is the LSP frequency ω ₁ ′, ω ₂ obtained in the immediately previous frame period, which is distributed and stored in the first to fourth registers B ₁ to B ₄ . ′,…, ω ₈ ′. Therefore, the above registers R ₁ , . . . , R ₄ and the above shift register
Due _{to the} eight shift _{operations of B 1} , _.
The calculations of △ _ω1 are performed sequentially, and the results of these 4-bit calculations are used as a new calculation in this frame period.
The LSP frequencies ω ₈ , ω ₇ , . . . , ω ₁ are distributed to the first to fourth shift registers B ₁ , _. That is, the contents of these shift registers B ₁ , ~, B ₄ are the LSP frequencies ω ₁ ′, ω ₂ ′, ..., in the immediately previous frame period.
The LSP frequencies ω ₁ , ω ₂ , . . . , ω ₈ in the frame period at this time are rewritten from ω ₈ ′.

In such a reading means, the parameter
Even if two types of frame areas F and F' coexist in ROM2, the above-mentioned cases () and () can be processed appropriately for each frame period. 1st to 4th shift register
B ₁ , ~B ₄ always have the following values in the frame period:
LSP frequencies ω ₁ , ω ₂ , ..., ω ₈ will be stored. Therefore, in the next subsequent frame period,
When performing the processing in the above case () or (), the LSP frequency ω of the frame period obtained sequentially as the shift output from the first to fourth shift registers B ₁ to B ₄ . ₁ , ω ₂ ,...
ω ₈ is supplied to a digital filter (not shown) that performs speech synthesis.

[Effects] As is clear from the above description, the speech synthesis device of the present invention converts a frame area consisting of a plurality of consecutive addresses of a parameter memory configured of N bits per address into a plurality of bits consisting of the n-th bit of each address. divided into N regions, and N LSP frequencies ω ₁ , ω ₂ , ..., are divided into N regions.
Either store ω _N respectively, or use the difference value △ω ₁ ,
Since △ω ₂ , ..., △ω _N are stored respectively,
In other words, since each LSP frequency can be stored in N areas obtained by vertically dividing the frame area with a width of 1 bit, data extraction processing can be set for each address of the memory, regardless of the number of bits of each LSP frequency. . Therefore, for example, even if a frame area storing the LSP frequency and a frame area storing the difference value exist together in the same parameter memory, reading in both frame areas can be performed using the reading means with the same configuration. It is possible to read out the LSP frequency or the difference value thereof, and it is hoped that the configuration of this type of speech synthesizer that employs the LSP method will be greatly simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a general speech synthesizer, FIG. 2 a and b are memory diagrams of the frame area in the parameter ROM used in the conventional speech synthesizer, and FIG. 3 is a block diagram showing the configuration of a conventional speech synthesizer. Memory diagram of the frame area in the parameter ROM of the speech synthesizer,
4a and 4b are memory diagrams showing an embodiment of the frame area in the parameter ROM of the speech synthesis device of the present invention, and FIG. 5 shows an embodiment of the configuration of the reading means used in the speech synthesis device of the present invention. FIG. 2...Parameter ROM, 3...Digital filter, F...Frame area, A...Adder, R
...Register, B...Shift register.

Claims (1)

[Claims] 1. N representing the characteristics of the voice extracted from the voice signal for each frame period that is considered as the steady period of the voice.
(>1) A set of LSP frequencies ω ₁ , ω ₂ , ..., ω _N are each quantized to a uniform number of bits, and stored in a frame area consisting of multiple addresses of a parameter memory configured with N bits per address. In an LSP-based speech synthesizer that reads these LSP frequencies from the parameter memory every frame period and resynthesizes speech, each frame of M×N bits consisting of M (>1) consecutive addresses in the parameter memory The area is
Each nth address (n=1, 2, 3,
…N) in a unit area of M bits consisting of bits
A speech synthesis device in which LSP frequencies ω ₁ , ω ₂ , . . . , ω _N quantized into M bits are stored in each unit area. 2 N representing the characteristics of the audio extracted from the audio signal for each frame period that is considered to be the steady period of the audio
(>1) The difference values Δω ₁ , Δω ₂ , ...Δω _N of a set of LSP frequencies ω ₁ , ω ₂ , ..., ω _N are each quantized to a uniform number of bits, and a parameter memory with 1 address and N bits is created. In an LSP-based speech synthesizer that resynthesizes speech by reading the difference values of these LSP frequencies from the parameter memory every frame period, Each frame area of m×N bits consisting of m (>1) addresses is
Each nth address (n=1, 2, 3,
…N) in a unit area of m bits consisting of bits N
Difference values Δω ₁ , Δω ₂ , quantized to m bits of each LSP frequency are divided into each unit area.
A speech synthesis device that stores ..., Δω _N.