JPH036728A - Disk device data transfer method - Google Patents

Abstract

PURPOSE:To increase the effective data transfer speed by transferring the data on plural disk devices in parallel and synchronously with each other. CONSTITUTION:The buffers 1a - 1b corresponding to plural disk devices and a buffer 1e corresponding to a host device are provided between these disk devices and the host device respectively. Then the waiting process is carried out for the transfer of data in accordance with the filled/empty states of those buffers between the disk devices and buffers 1a - 1d, between the buffers 1a - 1d and the buffer 1e, and between the buffer 1e and the host device respectively. Consequently, the synchronization is secured between the transfer of data to plural low-order disk devices and the transfer of data having the large data width to the high-order device. Thus it is possible to operate plural disk devices having the comparatively small data widths in parallel with each other and to add together these data widths for a disk device. Then the data having the large width can be transferred at the high speed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for controlling a plurality of disk devices by a controller, and in particular, it relates to a method for controlling a plurality of disk devices by a controller, and in particular, by synchronously transferring data from a plurality of disk devices under control in parallel. , relates to a data transfer method for a disk device that increases the effective data transfer speed.

[Conventional technology]

Conventionally, methods for controlling multiple disk devices by a controller include, for example, a method in which each disk device is configured with different data files having different logical addresses, or a method as described in Japanese Patent Laid-Open No. 63-56873. , the same information is stored in multiple disk devices, one is used as a mask, and the other is used as a backup (slave) when the mask is under load. Conventionally, there has been no discussion of a method in which a file is divided into bit slices and stored on multiple disks, and these disks are operated in parallel to synchronize and transfer data in parallel.

[Problem to be solved by the invention]

In the above conventional technology, even if multiple disk devices are used, the data transfer speed does not exceed the transfer speed of each disk device. It is necessary to increase the amount of data transferred per rotation (increase the bit density per track) or to increase the rotation speed of the disk device, which requires larger circuits and higher performance. This has led to problems such as the need to use expensive parts.

On the other hand, SC3I (Small Computer
System Interface), such as small disk devices, MCXCDROMs, printers, and CRTs.
It is a small computer system that composes multiple workstations such as playstations and exchanges data between them, and is made in accordance with the rules specified by ANSI (American National Standards Institute) and is compatible with various disk devices from various companies. An interface is used to enable common use of the following.

This SO3! There is the 5CSI-1 type interface, which has an 8-bit data bus and has a data transfer rate of about 1.5 Mbytes/sec in the first mode and 4 Mbytes/sec in the second mode. speed to 10
It is recommended to use a high-performance SCSI-2 type with increased speeds such as Mbytes/5eC1 or 40Mbytes/sec and widened data bus widths such as 16 bits, 24 bits, or 32 bits. . This SCSI-
Type 1 while maintaining compatibility with Type 5C5I-2 (i.e.
(while allowing SCSI-1 type and 5C5I-2 type to coexist)
If you try to upgrade, the circuit configuration on implementation will become extremely complicated. Juxtaposition on a device board is difficult and uneconomical.

Therefore, it is an object of the present invention to provide a disk device with a relatively narrow data bus width and a relatively slow data transfer rate (for example, an SC3I-1 with an 8-bit data bus width).
By synchronously operating multiple (for example, four) disk drives in parallel, it is possible to create a disk drive (for example, It is an object of the present invention to provide a data transfer method for a disk device that can easily configure a SCSI-2 type disk device W) having a 32-bit data bus width.

Another object of the present invention is to provide a data transfer method for a disk device that can be easily upgraded while maintaining compatibility with a SCSI-2 type disk device by using a plurality of 5C5I-1 type disk devices in parallel. There is a particular thing.

[Means to solve the problem]

In order to achieve the above object, the data transfer method for a disk device of the present invention includes means for operating a plurality of disk devices in parallel with an arbitrary transfer data width, and a means for operating a plurality of disk devices in parallel with a transfer data width corresponding to each disk device. A first input/output buffer section (an individual FIFO buffer provided on the disk device side) that corrects the transfer timing of each disk device, and a data width that is the sum of the transfer data width of each disk device, and A second input/output buffer section (common F provided on the upper device side) that is combined with the input/output buffer section and transfers data between the upper device and the added data width.
IFO buffer), and further includes data transmission/reception status between the first and second human output buffer units or a full or empty status of the first and second input/output buffer units. A means for performing transfer wait processing (transfer waiting processing) is provided.

Furthermore, a plurality of disk devices can be configured to perform synchronous operation by aligning their respective index marks.

In the preferred invention, each disk device is a 5C5I-1 type device with a data width of 8 bits, and by operating a plurality of disk devices in parallel, a 16-bit, 24-bit, or 32-bit wide SCSI - Configure a type 2 disk device subsystem.

[Effect]

The operation based on the above configuration will be explained.

By operating a plurality of disk devices in parallel, it is possible to make them function equivalent to a disk device whose data width is the sum of the data widths of the respective disk devices. As a result, it is possible to provide a device that can be used not only for a data width system of an individual disk device, such as the 5C5I-1 type, but also for an added data width system, such as the 5C5I-2 type. In this case, there is no need to separately provide the SCSI-1 type and 5CSI-2 type.

In addition, in the present invention, the above-mentioned first and second
By providing input/output buffer means, monitoring the full/empty state of these input/output buffer means, and performing wait processing corresponding to the state, transfer data of each disk device is transmitted to the host device as described above. It becomes possible to easily transfer the data width obtained by adding the width. That is, regarding data transfer between the lower-level disk device and the first input/output buffer means, a corresponding wait process is performed for each disk device, and data transfer between the higher-level disk device and the second input/output buffer means is performed. Regarding data transfer, corresponding wait processing is performed simultaneously for all devices.

To further explain this by dividing it into read and write times, when a full state of the input/output buffer means is detected for the device that is performing the earliest transfer (from the disk device to the first buffer means) during the read time, A wait process (waiting process) is applied to the disk device as soon as possible, and when an empty state of the input/output buffer means is detected for the slowest device at the time of reading, the process waits until the empty state is resolved.
Wait processing is applied to data transfer between the host device and the second buffer means. On the other hand, at the time of writing, if an empty state of the input/output buffer is detected for the fastest device (transferring from the first buffer means to the disk device), the input/output buffer is transferred from the first buffer means to the disk device until the empty state is resolved. When a full state of the input/output buffer is detected for the slowest device, a wait process is applied to the data transfer from the host device to the buffer means until the full state is resolved. In this way, transfer synchronization between the higher-level device and the lower-level device is performed, so that malfunctions do not occur.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.
Transfers by four disk devices #0 to #3, each having a data bus of (xX4) bits, are synchronized.
For example, a case where 32-bit data transfer is performed between a higher-order device and a lower-order disk device will be described. Note that although the diagram shows both upstream (transfer from a lower-level device to a higher-level device) and downstream (transfer from a higher-level device to a lower-level device), X and XX4 are one-way (direct).

In FIG. 1, 1. a, lb, lc, and ld are for disk device #0, disk device #1, and #1, respectively.
FIFO for disk device #2 and disk device #3
Control unit (F1rst in Fistouti
l1m part). In the following explanation, the disk device FIFO control unit 1a of #O will be mainly explained, but the disk device FIFO control units 1b to 1 of #1 to #3 will be explained.
ole, which has the same configuration and operation as d, is a FIFO control unit on the host device side.

For other blocks as well, subscripts a w d are added for #0 to #3 disk devices, and subscripts e are added for upper-level devices.
The configurations and operations common to these disk devices and host devices are indicated with subscripts a w d and e.
The explanation will be made using symbols excluding .

Also, regarding various signals, signals related to the upper host device are marked with H at the top, and signals related to the lower disk control device are marked with C at the top. A symbol is attached.

In FIG. 1, 2 (23 to 2e) is a RE Q/A CK transfer control unit, 3 (3a to 3e) is a parity checker, and 4 (4
a to 4e) are FIFO address counters, 5 (5a to 5
e) are FIFO buffers (for example, 58 to 5d are 5-stage shift registers with a data width of X = s = 3 bits, and 5e is a 5-stage shift register with a data width of XX4 = 32 bits), 10e) is the m signal, that is, the request signal issued by the disk control device (- indicates negative logic, the same applies hereinafter), 11 (lla to 1i
e) is the DATA signal, that is, the data signal, 12 (12a
~12e) is the Xτ signal, that is, the A issued by the higher-level device
cknow1edge signal (acceptance, notification signal), 13
(13a to 13d, 13e) are interfaces and FI
Transfer data to/from FO buffer, 14 (14a to 14
e) is the address count timing signal, 15 (15a
~15e) is the address count output signal, 16 (16a)
-16d) are the transfer data between the FIFO buffer for each lower disk device and the FIFO buffer for the upper host device, and 17 is the TWAIT signal (17a-18
d is an ACWAIT signal, 17e is a REQ WAIT signal), 18 (18a" 18e) is data separated from upper device data, 20 (20a to 20d) is a data comparison device, 21 (21a to 21e) is a PER signal, i.e. Parity error signal, 22 is FIFO MA
X address signal, 23 (23a to 23e) is CM
This is the P signal, that is, the address comparison timing signal.

FIG. 2 shows each FIFO 1i11 [parts 1a to 1d] in FIG.
FIG. 2 is a signal waveform diagram showing access timing common to FIG. In the same figure (a), when reading from the perspective of the host device, that is,
When data is read from a disk device and transferred to a higher-level device, FIG. 2B is a write time from the perspective of the higher-level device, that is, when data transferred from the higher-level device is written to the disk device. When reading, data is transferred from the lower device to the higher device at the same time as the request signal is issued, and when the higher device receives the data, it returns an ACK signal.
On the other hand, at the time of writing, when the higher-level device prepares data in response to the request signal, it returns an ACK signal and also transfers the data from the higher-level device to the lower-level device.

At the time of reading, the data width x (-8) bits, that is, 1 byte width data read by each disk device #O to #3 enters the FIFO control section l door section 1d, where each 1 byte of data is read. Shift register type FIFO buffers 5a to 5 that can hold data of several bytes (in the figure, 5 stages, that is, 5 bytes) of data in the order of input.
d. The outputs of the individual FIFO buffers 5a to 5d enter the FIFO control unit 1e, where they are sent to XX4(-
32) A common F that has a data width of bits and can hold data for several times that bit (in the figure, 5 stages, that is, 5 times) in input order.
The signal is input to the IFO buffer 5e. The outputs 18a to 18d of the common FIFO buffer 5C are XX4 (32)
It is combined with bit-width data 13e and output to a host device.

When writing, data is transferred in the opposite direction to when reading (from right to left in FIG. 1).

Data transferred by one REQ/ACK signal, that is, from one REQ/ACK signal to the next REQ/AC
The amount of data sent up to the Q signal is divided into 8 x 4 bits by buffer registers 53 to 5d or buffer register 5e.
), but to increase the data transfer speed,
For each REQ/ACQ signal, buffer register 5a~
It is better to transfer data for several stages of 5d or 5e in succession.

3(a) and 3(b) are block diagrams showing the detailed configuration of the data control system in FIG.
K transfer control unit 2a, variation checker 3a, and FIF
It almost corresponds to a circuit consisting of the O address counter 4a and one stage of the FIFO buffer 5a. Figure (a) shows the circuit configuration when reading data (when transferring data from a lower-level device to a higher-level device), and Figure (b) shows the circuit configuration when writing data (when transferring data from a higher-level device to a lower-level device). . In the same figure, 27-1 and 27-2 are lower interface data latch circuits composed of flip-flop circuits.
This and logic gates Nl, NA1, NIL, NOI, O
R1, N4. The portion including the timing circuit including the delay element DL3 and the like almost corresponds to the RE Q/A CK transfer control section 2a in FIG. Also, parity checker 3 and logic element N2. AI, NA2. NA3. Delay element DL 1. A timing circuit portion including flip-flops FF and the like substantially corresponds to the parity checker 3a in FIG. Furthermore, counters 4-1 and 4-2 correspond to FIFO address counter 4a in FIG. 28-1
and 28-2 are upper-level interface data latches constructed of flip-flop circuits, which roughly correspond to the FIFO buffer 5a in FIG.

Figures 4(a) and 4(b) are timing waveform diagrams of signals at each part in Figures 3(a) and (b), with Figure 4(a) showing the time when data is received and Figure 4(b) showing the time when data is being sent. show. In Figures 2 to 4, 26 (26-1°26-2.26a ~
26d) is an address count output signal (corresponding to 15 in FIG. 1), 29 (29-1, 29-2) is a DLTH signal, that is, an interface data latch timing signal,
30 is a parity check timing signal PCHK. In addition, the subscript -1 after the numbers in Figures 3 and 4
, -2 indicate that the common signal is used during reading and writing, respectively.

FIG. 5 is a detailed circuit configuration diagram of the data comparison device 20 shown in FIG. 1 (that is, the transfer control unit of the data transfer FIFOs 5a to 5d of each disk device and the data transfer PIF 05e of the host device). In FIG. 5, the transfer control unit of disk device #O is shown in detail at 20a, and disk device #1
The configuration within the block of the transfer control units 20b to 20d of ~#3 is also the same as that of 2°a. In the same figure, 01 to G1o are logic gates, 24a is a FIFO full signal, and 25a is an FIFO
FO empty signal, 34 (34a to 34d) is an address comparison circuit, 31 is a high level READ M at the time of reading.
ODE signal, 32 is high level WRITE when writing
MODE signal 33 (333-33d) is a comparison timing signal that provides the comparison time point of the address comparison circuit 34;
35 (353-35d) is a full signal indicating that the FIFO buffer is full, 36 (36a-36d)
is an empty signal indicating that the FIFO buffer is empty,
37 (37a to 37d) are similar full signals when reading, 38 (38a to 38d) are similar empty signals when writing, 39 (39a to 39d) are similar empty signals when reading signals, and 40 (40a to 38d) are similar empty signals when reading. 40d) is a similar full signal at the time of writing, 41 (41a to 41d)
is the WAIT signal sent to the host device.

Next, the operation of this embodiment will be explained using FIGS. 1 to 5.

When receiving data from the disk device (reading), disk device #n (#O to #3) sets data 11 and then reads the data as shown in FIG. 2(a) or FIG. 4(a).
Turn on signal 10 at I-D (falling part of waveform 10 in the figure)
, After the data is fetched and confirmed by the data control logic unit (REQ/ACK transfer control unit) 2, ■]] ball signal 12
(waveform 12 falls in the figure). Read data 11-1 is -■] “τ1 from turning on (falling edge) of σ signal
The interface data latch timing signal (DLTH signal) 29 is guaranteed until the signal turns on (falling edge).
-1 is turned on, the data is latched in the lower interface data latch circuit 27-1, and then the parity checker 3 performs a parity check on the data. The output ■π1 of the parity checker is a parity check timing signal. The timing is adjusted by PCHK30, and the parity error signal PER21 is taken out from the FF. Furthermore, after the data is latched into the flip-flop 27-1, the count value 26-1 of the address counter 4-1 is increased via the logic gate NA3 at the timing when the timing signal PCHK30 is turned on (high level), but the error PER21 When this occurs, the logic gate NA3 is turned off to stop the counter 4-1 from counting. If there is no error, the data is taken in (latched) into the FIFO buffer 5 (upper interface data latch 28-1) and the address count value for address comparison is increased. Thereafter, when the m signal ends (falls), the address comparison timing signal CMP23 is generated by the logic gate A2, and address comparison is performed as described later at the timing when the signal is turned on (high level).

On the other hand, when sending data to the disk device (writing), as shown in FIG. 2(b) and FIG. 4(b),
Disk device #n (#O to #3) makes a data transfer request by turning on (falling down) the m signal 10. In response to this request, it reads data from the upper FIFO buffer (5e) in advance and transfers it to the flip-flop 2B- 2 (individual, lower F
The data latched in the IFO buffers 5a to 5d) is transferred to the flip-flop 2 at the timing of the timing signal DLTH29-2 which falls simultaneously with the τm signal 12.
7-2, and from this point on, it is sent out to the disk device as write data 11-2. The data 11-2 is guaranteed during the period (signal 32) when both the τm signal 12 and the r-100 signal 11 are on (low level).

When multiple byte data lie is read or written from the upper host device to the multiple byte FIFO buffer 5e, it is similarly realized using the block diagram of FIG. 3 and the timing of FIG. 4.

Now, referring to FIG. 5 and FIG. 2, the operation of data transfer based on address comparison between each disk device and the host device will be explained. Address comparison timing is shown in FIG.

At the timing when the τππ signals 10a to 10d of each disk device turn off (rise), the timing signal CMP
23), the count values 26a to 26 of the FIFO buffers 5a to 5d of each disk device
d and the count value 26 of the FIFO buffer 5e of the host device
e is compared by the address comparison circuit 34 (34a to 34d).

Note that the count values (i.e., addresses) 26a to 26d and the count value 26e are expressed as a, a+1, . . . in FIG.
..., b, b+l, ..., etc., and the fifth
In the figure, they are shown as A and B. Here, A is the individual address of the last data input to each of the individual FIFO buffers 53 to 5d at the time of reading (the address of the previous data to be outputted first from each of the individual FIFO buffers 5a to 5d at the time of writing) individual address), B is
This is the common address of the data to be outputted first from the common FIFO buffer 5e at the time of reading (the common address of the data to be input last to the common FIFO buffer 5e at the time of writing). Therefore, C represents the data length held through individual and common FIFO buffers for each disk device. Comparison result C is obtained by C=I B-A I. When the value of C reaches a predetermined maximum value, the FIFO buffer is full, and a full signal 35 (35a to 35d) is generated. At C-0, the FIFO buffer is empty, and an empty signal 36 (36a to 36d) is generated.

When reading from a host device, rather than transferring data from the common FIFO buffer 5e to the host device,
Individual FIFO buffers 5a to 5d from the lower disk device
When the data transfer to one of them is faster, the value of the comparison result C increases, and when this value reaches the maximum value of 22 of the FIFO buffer address, the full signal 3
5a-35d, logic game) 02. G4. ACK wait signal (ACKWA IT) 17 (17
a=17d), thereby stopping the timing of turning off the seven signals 12a to 12d at τ, as shown by the dotted line C6 in FIG. 2(a). As a result, as shown by the dotted line CI' in FIG. 2(a), the signals 10a-10d are not generated in the next π by the lower-level device, and as a result, the full state of the FIFO buffer is released.

Conversely, in the case of reading, the FIFO is read from the lower disk device.
Transfer from the flFo buffer to the host device is faster than transfer to the buffer, and when the FIFO buffer becomes empty, C=O and the empty signal 36 (36a to 36
d) occurs and logic gate G3. G5. R via G9
EQ WAIT signal 41 (41a to 41d) (
17e) and tiREQ WA ■ T signal 41 (1
7e), as shown by the dotted line ct in FIG. 2(a),
The signal 10e is not turned on at the next π to the host device. As a result, the ■τff signal 12e is not generated, as indicated by the dotted line 02' in FIG. 2(b).

As a result, transfer synchronization between the higher-level device and the lower-level device is maintained.

Also, according to the above configuration, F from multiple disk devices
If there is a lag in the timing of transfer of read data to the IFO buffer, and the transfer from one disk device is later than the others, the transfer from the PIFO buffer to the host device for the data that was transferred earlier will be delayed. When the transfer from all disk devices including those that are delayed to the FIFO buffer is completed, the transfer from the FIFO buffer to the higher-level device is performed at the same time, and thus the disk device The skew error between the two can be removed.

On the other hand, in the case of writing, when the FIFO buffer becomes empty, the logic gates G3°G7 . ACT WAIT signal l7 (173-17d) via G8
τ and T for the lower disk device.
When the signals 12a to 12d are stopped and, conversely, the FIFO buffer reaches MAX (that is, when it is full),
Logic gate G2. G6. G9. The signal 10g is stopped at π to the lower-level device via the GIO.

The other operations are the same as when reading (Fig. 2(b)
reference).

The conditions for determining that the FIFO buffer is empty and the conditions for determining that the FIFO buffer has reached MAX may be set several bytes before each to absorb program overhead, transfer time, and the like.

The capacity (number of stages) of the FIFO buffer should at least absorb the above-mentioned overhead and transfer time, absorb skew errors between each disk device, and wait until data transfer is stopped after detecting a full/empty state. A sufficient number of stages is required to absorb and hold the excessively transferred data that is currently being transferred.

By using the technology of the synchronous operation method of multiple magnetic disk drives according to the above-mentioned Japanese Patent Application No. 63-60519, if the index marks of each disk drive are aligned and the disks are operated synchronously, the skew between the disk drives can be reduced. Since the error is small, the capacity (number of stages) of the FIFO buffer may be small.

On the other hand, when writing or reading is performed without aligning index marks between disk devices, it is necessary to align data between disk devices at arbitrary rotational phases (to eliminate skew errors). Therefore, a FIFO buffer with a maximum number of stages corresponding to one track (one rotation) of the disk is required.

In the above embodiment, the disk device 4 has a data width of 8 bits.
The machine transfers data with a width of 32 bits, but by using only the data for one, two, or three machines at any time and discarding the other data, it is possible to transfer data with a width of 8 bits or 16 bits. It is also possible to process data of any width, such as , 24-bit, or 32-bit width.

Also, for example, if you use two 8-bit wide disk devices, one as a mask and the other as a slave, you can use them as a double file, and when writing, the upper 8 bits and lower 8 bits of the 16 bits are written as the same data. There is a method to transfer the data as 8 bits and receive the required 8 bits when reading, a method to compare the upper 8 bits and lower 8 bits to confirm that there are no read errors, and a method to check and correct errors in several of multiple devices. The method for data can also be used in combination with the above embodiment.

In the above embodiment, the full/empty state is detected through the buffer means 5a to 5d and the second buffer means 5e in FIG. 1, but the full/empty state of the first buffer means 5a to 5d is The full/empty state of the second buffer means 5e is separately detected, and depending on the state, between the disk device and the first buffer, between the first buffer and the second buffer, or between the second buffer and the host device. It is also possible to perform either transfer weight control.

〔Effect of the invention〕

As explained in detail above, according to the data transfer method of the disk device of the present invention, arbitrary plural disk devices having a relatively narrow data width such as the SC3I-1 type can be operated in parallel. , for SCSI-1 and S
It is possible to function as a disk device with a data width that is the sum of the data widths of those for CSI-2 without having to place them side by side.
For example, it has the effect of being able to transfer data with a wide data width at high speed, such as in a SCSI-2 type system.

Also, between these multiple disk devices and the host device,
A first (individual) buffer means corresponding to each disk device and a second (common) buffer means corresponding to the host device are provided, and the disk device and the second buffer means are provided according to the full/empty state of these buffer means. Since data transfer wait processing is performed between one buffer means, between the first buffer means and the second buffer means, or between the second buffer means and the higher-level device, the lower-level This has the effect of being able to synchronize data transfer between a plurality of disk devices and data transfer with a wide data width to a host device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIGS. 2(a) and (b) are timing waveform diagrams of signals during reading and writing, and FIGS. 3(a) and (b) are Figure 1 is a circuit diagram showing details of the FIFO control block (data control system), Figure 4 (a) and (b) are timing waveform diagrams of signals in each part of Figure 3 (a) and (b), and Figure 5 is a diagram showing the details of the FIFO control block (data control system). FIG. 2 is a circuit diagram showing a detailed configuration of the data comparison device of FIG. 1; 1 (1a-16>...F I FO control unit, 2 (2a-2e)...RE Q/
A CK transfer control unit, 3 (3a to 3e)...
... Parity Chekka, 4 (4a-46)...
...FIFO address counter, 5 (5a ~ 5
e) FIFO buffer, 10 (10-10e)...
...1go "σ signal, 11 (lla~11e...
......Data signal (transfer data), 12 (12a
~12 e) ・-・・・:・ACK signal, 13(1
3a-13e)...Transfer data, 14
(14a=14e)...Address count timing signal, 15 (153-15e)...
...Address count output signal, 16 (16a to 1
6d)......Transfer data, 17 (17
a ~17 e) ”-”TT”'iff/Xr■WA
IT signal, 18 (18a-l8e) =-=transfer data, 20 (20a-20d)...
Data comparison device, 21 (21a to 21e)...
...Parity error signal, 22...
FIFO MAX address signal, 23 (23a to 2
3e) Address comparison timing signal, 24 (24a to 24d)-----F I F
O full signal, 25 (25a to 25d)...
...FIFO empty signal, 26 (26-1, 26-
2, 26a to 26d)... Address count output signal, 29 (29-1, 29-1)...
......Interface data latch timing signal, 30...Parity check signal, 31
......Signal indicating read time, 32...
... Signal indicating write time, 33 (33a to 33d
)......Comparison timing signal, 34...
...Address comparison circuit, 35...
・FIFO full signal, 36... FIFO
Empty signal, 37... Same full signal (when reading), 38... Same empty signal (when writing)
, 39... Same empty signal (when reading), 4
0......Full signal (when writing). Agent: Patent attorney Kenji Takeshi (1 other person) Figure 4

Claims (1)

[Claims] 1. Means for operating a plurality of disk devices having arbitrary transfer data widths in parallel, and means for correcting the transfer timing of each disk device with the transfer data width corresponding to each disk device. The first input/output buffer section has a data width that is the sum of the transfer data width of each disk device, and is combined with the first input/output buffer section, and transfers data between the host device and the host device using the added data width. The data transmission/reception state between the second input/output buffer section for performing transfer and the first and second input/output buffer sections, or the first,
1. A data transfer device for a disk drive, comprising means for performing wait processing for data transfer in response to a full or empty state of a second input/output buffer unit. 2. The data transfer method for a disk device according to claim 1, wherein the plurality of disk devices are configured to perform synchronous operation by aligning their respective index marks. 3. Each of the plurality of disk devices has a SCSI-1 type data width, and the added data width is the SCSI-1 type data width.
3. The data transfer method for a disk device according to claim 1, wherein the data width is adapted to type -2.