JPH036739U - - Google Patents
Info
- Publication number
- JPH036739U JPH036739U JP6759089U JP6759089U JPH036739U JP H036739 U JPH036739 U JP H036739U JP 6759089 U JP6759089 U JP 6759089U JP 6759089 U JP6759089 U JP 6759089U JP H036739 U JPH036739 U JP H036739U
- Authority
- JP
- Japan
- Prior art keywords
- address
- line
- workstation
- address decode
- decoded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Description
第1図は、本考案の一実施例を示すブロツク図
である。
1……アドレスドデコード回路、2……I/O
アドレス設定回路、3……OR回路、4……OR
回路。
FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Addressed decode circuit, 2...I/O
Address setting circuit, 3...OR circuit, 4...OR
circuit.
Claims (1)
続する手段と、デコードしたいアドレスを自由に
変更できる手段と、ワークステーシヨンからのI
/Oアドレスを比較するアドレスデコード回路を
有するI/Oアドレスデコードボード。 A means for connecting to the address line and control line of the workstation, a means for freely changing the address to be decoded, and an I/O line from the workstation.
An I/O address decode board having an address decode circuit that compares /O addresses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6759089U JPH036739U (en) | 1989-06-08 | 1989-06-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6759089U JPH036739U (en) | 1989-06-08 | 1989-06-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH036739U true JPH036739U (en) | 1991-01-23 |
Family
ID=31601292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6759089U Pending JPH036739U (en) | 1989-06-08 | 1989-06-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH036739U (en) |
-
1989
- 1989-06-08 JP JP6759089U patent/JPH036739U/ja active Pending
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