JPH0368023A - Electronic computer - Google Patents

Abstract

PURPOSE:To suppress the reduction of reliability to the minimum by storing all loading programs in ROM, coupling a patch program on a RAM from an inlet position of a subroutine and executing it by a branch destination control program. CONSTITUTION:A loading program 5 stored in ROM 2 is read successively through a bus 4, and brought to decoding processing by a CPU 1. A working area 6 on a RAM 3 is used as a storing place, a stacking area, etc., for a vari able parameter and intermediate data under the control of the CPU 1. In the case of the regular execution, the loading program 5 executes an application program 13. Subsequently, by a program re-write requesting command of a ground station, a patch program writing program 12 and branch destination address writing program 10 are executed. Next, by the program 12, a patch program 29 is loaded on the space area 7 of the RAM 3.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is applicable to computers installed in artificial satellites, spacecraft, space bases, etc., which are exposed to radiation and in environments where computer maintenance is not easy. It is related to.

[Conventional technology]

Conventional electronic computers can be broadly classified into two types. Figure 4 is a diagram showing a typical configuration of an electronic computer based on readable/writable memory, which is the first type of conventional electronic computer.
Abbreviated as σ. ), logging) is read-only memory (hereinafter referred to as RO)
Abbreviated as M. ), (□□□ is read/write memory (hereinafter referred to as
Abbreviated as RAM. ).

(41d bus (data bus, address bus,
l [consists of a control bus], (51 is RAM and some RO
The installed program stored in M, (6) is RAM +
3) Upper work area (including stack area), (7
) is a space area on RAM (3). Although not shown in the diagram, there is also an I10 interface and power supply.

Clock, DM (Direct Memory Ac)
cess) :Y controller 1 There are many cases in which a small interrupt processing circuit, a safety circuit, etc. are added, but they are omitted here because they are not directly related to this invention.

Figure 5 is a diagram showing a typical configuration of a conventional electronic computer of the g20 type, which is a computer mainly based on read-only memory.
M, (31 is RAM, (41 is bus, (5) is ROM
Onboard program stored in +21, (6) is RAM
(Work area on 31 (including stack area),
m&-) The operation of these electronic computers in the 0th order, which is the space area on RAM+31! 12 light・uOM+2
The onboard program stored in 1t or RAM + 3) is O.
The data is sequentially read out by the P U (1) via the bus (4), decoded and processed, and performs various functions required of the electronic computer, such as input/output data processing, control calculation, and failure detection. At this time, storage locations for variable parameters and temporary data,
A work area (6) on RAM +31 is used as a stack save area as appropriate under the control of OP [r (1).

[Problem to be solved by the invention]

The first type of conventional electronic computer, a RAM (3) based computer, uses RA based on commands from the ground station.
The onboard program stored on M+31 was rewritten in orbit, and the spare area was used to apply a batch to the onboard program. So-called in-orbit reprogramming was possible. Therefore.

It was possible to flexibly deal with changes to the onboard program due to problems in orbit. On the other hand, many of the semiconductor devices currently used in space RAM have weak protection against radiation.

LL Bit status is reversed by writing on the road. This method has a major drawback in that so-called single event errors often occur. For this reason, radiation shielding measures are required, but since complete prevention is impossible, many of this type of electronic computers are equipped with high RQ to protect critical programs and parameters from radiation.
Store it in M.

When an error occurred, measures were taken such as temporarily transitioning to a safe control mode using the program in ROM, and then reloading the program to RAM. However, during this time, it was inevitable that the mission would be interrupted, albeit temporarily. Also.

In order to retain the program in the RAM, it is necessary to constantly supply power to the RAy.In the event of a failure such as an interruption in the power supply, it is necessary to reload the program to the RAM after the failure is recovered.The same measures as above are required. Even if this was done, it was inevitable that the mission would be interrupted, albeit temporarily.

On the other hand, the second type of ROM-based computer is
Energy level required for bit inversion of ROM d RA
Since it is much higher than M, single event errors due to radiation are not a problem, and in this respect it is characterized by high reliability. However, since all onboard programs are written in ROM, in-orbit reprogramming is generally impossible, and program changes or additions due to unexpected malfunctions in orbit, or program changes due to changes in mission requirements. It also had the disadvantage of not being able to respond flexibly to additions.

This invention was made to solve the above-mentioned problems in conventional electronic computers, and has the high reliability against radiation that conventional ROM-based computers have, and the in-orbit reprogramming function that RAM-based computers have. This is an electronic computer that has system flexibility due to system flexibility, and can minimize the reliability that decreases due to system flexibility by setting patch programs stored in RAM for each subroutine. The purpose is to obtain.

[Means to solve the problem]

In the computer according to the present invention, the setting position of the breakpoint on the installed program is limited to the beginning of the subroutine, and the setting position is set as the subroutine breakpoint,
RAMK is the branch destination address to jump from the subroutine breakpoint to the patch program placed in RAM.
Branch destination address writing program with writing function.

A breakpoint flag writing program that has a function of writing a breakpoint flag to RAM that determines whether or not there is a branch from a subroutine breakpoint to a patch program; and a patch program writing program that has a function of writing three patch programs to RAM; After execution of the subroutine call instruction, only when the breakpoint in the breakpoint flag area indicates execution of a branch to the patch program, the value of the branch destination address corresponding to the breakpoint flag in the branch destination address area is written to the program address area. Place the installed program including the branch destination control program to be set on the ROM.

Also, on the RAM, there is a branch destination address area for writing the branch destination address as bait for the branch destination address writing program, a breakpoint flag area for the breakpoint flag writing program to write a breakpoint flag, and a breakpoint flag area for writing the breakpoint flag by the breakpoint flag writing program. It is equipped with a batch area for writing patch programs.

[Effect]

The electronic computer according to the present invention stores all the installed programs in the ROM, and stores them in the branch destination control program.
The patch program on the RAM corresponding to the subroutine of the onboard program is combined and executed from the subroutine position of the onboard program.

This enables in-orbit reprogramming.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

Figure +81 is a block diagram of the electronic computer of this invention.

The installed program (5) stored in the ROM (2) is sequentially read out via the bus (4) and decoded and processed by apσ (1). Rh M (31 work areas (6) are
It is used as a storage place for variable parameters and intermediate data, a stack area, etc. under the control of apσ(1). Also, the space area (7) is 0F for storing patch programs.
Used under the control of U(1).

During normal execution, the onboard program (5) does not execute the 3 patch program writing program (LlJ, branch destination address writing program a) and breakpoint flag writing program, but only executes the application program (I3). Reprogram write request command, etc. 3 patch program write program 0 and branch destination address write program (LI is executed and 3 patch program write program a3, 1) A command, etc. is sent to the space area (7) of RAM +31. The sent patch program (2) is loaded and the branch destination address write program 0O
The start address of the patch program (to) is written in the branch destination address area (8) of RAM +31. Next, use the ground station's reprogram execution command, etc. to write the break point flag writing program α2.
) dK executed, breakpoint flag area (9)
The breakpoint flag is written as on or off. During execution of an application program, a breakpoint flag area (9) is sent to the branch destination control program every time a subroutine call instruction is read.
Refer to the breakpoint flag specific to the called subroutine that is set to 1, and if it is on, set the branch destination address specific to the called subroutine in the program counter, and change the flow of execution to RAM ( 3
Move it to the patch program screen above.

Further, if it is off, the value of the program counter is not changed, and the execution flow does not change between the installed program (5) stored in iJ ROM +21 and bB.

Figure 2 is a flowchart of the processing of the electronic subtraction machine of this invention.
This will be explained in detail using this figure.

After starting in step αa, the onboard program (5) judges whether there is a reprogramming request or not in step (l!9), and writes the 3 patch program only if there is a reprogramming request command from the ground station. Program O and branch destination address writing program αG are executed.
JRA using patch program writing program α2
M+31 space area (patch program (29a) sent to 71 as a command etc., (29t
l) l... is loaded and the patch program (29a) l (29b )? ...
The branch destination address (28a), (28b),
... will write and meet. Next, the presence or absence of a reprogram execution request is determined in step aO, the breakpoint flag writing program U is executed, and a subroutine-specific breakpoint flag is written in the breakpoint flag area (9) by the reprogramming execution request command from the ground station. (27a), (27b), . . . are convolved as on or off.

When the subroutine call instruction (13a) of the application program α3 is executed, the value of the program counter is stacked in the stack area O1 of the work area (6). Processing then moves to a subroutine (arrow 30)
, the branch light control program α2) is called (arrow 31
), the process is started in step 翑. First, refer to the breakpoint flag area (9) and set the breakpoint flag (27a) specific to the called subroutine.
The on/off state is determined in step CO.

If it is off at step Qll, the process ends at step αD without changing the value of the program counter, and the subroutine process continues (arrow 32).

The next instruction (13b) in the subroutine is executed next. Then, by executing the subroutine return instruction (1SC), which is the last instruction in the subroutine, processing continues to the instruction (13a) following the first subroutine call instruction (13a) (arrow 35).

On the other hand, if step 21) K> is on, the branch destination address (28 &) specific to the branch routine in the branch destination address area (8) is set to the program counter.
3, and end the process with step a force.0 As a result, the flow of processing is RAM
The program moves on to the patch programs ('9a), (29b), . . . that were sent as commands to 71 (arrow 53). In the example in this figure, the subroutine call instruction (1
This is the case where the branch destination address specific to the subroutine called in 30 points to the start address of the patch program (29a) and Lnfc. The instruction at the address indicated by the program counter is the first instruction of the patch program (29a) and is read next. Therefore, it is possible to run patch programs. Then, by making the last instruction of the patch program (2S'a) a subroutine return instruction, the program counter is changed to the value stacked in the stack area @O of the work area (7) + 2, and the flow of processing is Move to the next instruction (13d) after the subroutine call instruction (13a) of application program 3 on ROM +21 (arrow 34)
.

Assuming that the above processing flow is a cycle of execution of the subroutine call instruction of the application program αj, once all the instructions of the application program α3 have been processed, the execution of one cycle of the installed program (5) ends at step a9.

FIG. 3 will be described in detail with reference to a flowchart of processing of an electronic computer showing another embodiment of the present invention.

After executing patch program writing program α2.

Perform a parity check of the patch program written in the parity check program (c), and set the parity check flag to OFF if the result is normal, and ON if the result is abnormal, to parity check area 4 of work area (6).
Write in 1). Then, the execution of the branch destination control program is pressed, and with reference to the parity check area (4D), it is determined in steps whether the parity check flag is on or off.

If the parity check flag is on in step @, the process continues at step αD without changing the value of the program counter.
to exit and continue the subroutine processing (arrow 32),
The next instruction (13b) in the subroutine is executed next. Then, by executing the subroutine return instruction (150), which is the last instruction in the subroutine, processing continues to the instruction (1)) following the subroutine call instruction (13a) (arrow 35).

On the other hand, if the parity check flag is off in step @, the breakpoint flag area (9) is referenced first, and it is determined in step QD whether the breakpoint flag (27a) specific to the called subroutine is on or off.

Further, processing of an electronic computer showing still another embodiment of the present invention will be explained using FIG. 2.

In Figure 2, branch destination address writing program a
The branch destination address (28a), (28b), which is written to the branch destination address area when executing ・
... is 3 consecutive words of the same address data, 1
! ! 7. Similarly, the breakpoint flags (27a), (27b), etc. written to the breakpoint flag area (9) of RAM f3+ by executing the breakpoint flag writing program α2l are also the same on/off flags for three consecutive words. It becomes what it is. Then, the on/off determination of the break point flag (Z7a) applied to the branch destination control program +141 is performed (step e
i+ ) reference to the breakpoint flag.

When the determination result is on, reference to the branch destination address is performed by majority decision.

〔Effect of the invention〕

As described above, by storing the installed program in the ROM according to the present invention, high reliability against single event errors and power supply interruptions can be obtained, and the subroutine of the installed program in the j5ROM can be controlled by the branch destination control program. It is possible to change the flow of execution from the input port to the RAM patch program.
AM patch programs can be easily constructed based on the required functions, allowing reprogramming with minimal deterioration in reliability and providing high flexibility to the system, such as changing programs due to changes in mission requirements. There is an effect that can be obtained.

In addition, according to this invention, by adding logic that does not execute the patch program when there is an abnormality in the patch program constructed by commands etc. from the ground, it is possible to prevent system command transmission errors and command reception errors. This also has the effect of further increasing the reliability of command data conversion.

Furthermore, in this invention, the branch destination address area and the breakpoint flag area of the RAM are made into a triple system, and the reading thereof is decided by majority decision.
This has the effect of making it possible to eliminate misinterpretation of addresses and flags due to single event errors in these areas, and further increasing the reliability of the system against single event errors.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an electronic computer according to an embodiment of the invention, and FIG. 2 is a configuration diagram showing an electronic computer according to an embodiment of the invention. FIG. 3 is a flowchart showing details of the operation of a computer according to a third embodiment of the present invention. FIG. FIG. 5 is a block diagram of a conventional ROM-based electronic computer. In the diagram, (1) BaC! PU, 12) is ROM (31
is RAM, (41 is bus, (5) is installed program, (
6) is the work area, (7) is the space area, (8)
is the branch destination address area, (91 is the breakpoint flag area, ■ is the stack area, (4D is the parity check area, α is the branch destination address writing program, an is the breakpoint flag writing program, α2 is the patch program writing program, αj is an application program, a- is a branch destination control program, @ is a parity check program, and G!I is a patch program.Identical or equivalent parts in the figures are indicated by the same reference numerals.

Claims (3)

[Claims] (1) In an electronic computer consisting of a central processing unit that controls processing, a read-only memory for data, and a memory that allows data to be read and written, the above data can be read and written in the read-only memory for the above data. An area where you can write a program that writes a patch program to memory, an area where you can write a program that writes a branch destination address from the breakpoint subroutine to memory that allows you to read and write the above data, and a breakpoint to memory that allows you to read and write the above data. An area where you can write a program to write a breakpoint flag that controls whether or not there is a branch in the subroutine, and a branch destination from the breakpoint subroutine by referring to the breakpoint flag on the read/write memory of the above data when calling the subroutine. It has an area where a control program can be written, and also has a read/write memory for the above data.
An area for writing the above branch destination address, an area for writing the above breakpoint flag, and 3
An electronic computer having an area for writing patch programs. (2) In the read-only memory for the above data, there is an area where you can write a program that performs a parity check of the patch program on the read/write memory for the above data, and when a subroutine call is made, the result of the parity check is 2. The electronic computer according to claim 1, further comprising an area in which a program for controlling a branch destination from a breakpoint subroutine can be written. (3) In the read-only memory for the above data, write an area where you can write a program that writes the branch destination address as a triple system in the read/write memory for the data, and a program that writes the breakpoint flag as a triple system. and an area where a program can be written that determines the data to be quoted from the above-mentioned read/write memory by majority vote of the data in the three memories. 2. The electronic computer according to claim 1, further comprising an area for writing the branch destination address memory as a triple system, and an area for writing the breakpoint flag memory as a triple system.