JPH0368038A - Information processor - Google Patents

Abstract

PURPOSE:To speed up for retesting an instruction by selecting one of first and second scan paths corresponding to an instruction from a diagnostic device. CONSTITUTION:A diagnostic controller 1 is equipped with a peculiar diagnostic control software and executes the fault processing, etc., of an arithmetic processing unit 2 by this diagnostic control software. When a fault is generated in the arithmetic processing unit 2 under operation and the retest of the instruction is executed by the arithmetic processing unit 2 under the control of the diagnostic controller 1, it is necessary to check justifiability for the contents of software visible register groups 31a-31d in the arithmetic processing unit 2 and to write the contents back to the register groups 31a-31d. At such a time, the diagnostic controller 1 makes the scan path in the arithmetic processing unit 2 effective.

Description

TECHNICAL FIELD The present invention relates to an information processing device, and more particularly to an information processing device that retries an instruction when a failure occurs.

BACKGROUND ART Conventionally, in this type of information processing device, all flip-flops (hereinafter referred to as FFs) of packages related to software visible registers whose validity needs to be checked when retrying instructions of the arithmetic processing device are used. The contents are read using a scan path, and a portion necessary for the software visible register is extracted from the contents of the read FF to check its validity.

After this, the contents of those FFs are written back using the scan path used for reading.

In such a conventional information processing device, when reading the contents of a software visible register group whose validity needs to be checked when retrying an instruction of the arithmetic processing unit, the FF of the software visible register group exists. Since the entire campus is scanned out, the contents of FFs unrelated to the software visible register group are also scanned out, which has the disadvantage that it takes time for the arithmetic processing unit to retry instructions.

OBJECTS OF THE INVENTION The present invention was made in order to eliminate the drawbacks of the conventional ones as described above, and an object of the present invention is to provide an information processing device that can speed up instruction retry.

Configuration of the Invention An information processing device according to the present invention is configured by cascading each of a plurality of registers in the device, and has a first scan path that can be freely scanned in and scanned out from a diagnostic device, A second scan path configured by cascading a group of registers whose validity needs to be confirmed at the time of retrying an instruction among the plurality of registers; and one of the first and second scan paths. The present invention is characterized in that it has a selection means for selecting according to an instruction signal from the diagnostic device.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, a diagnostic control device 1 includes a scan path/instruction retry control unit (hereinafter referred to as the control unit) O that controls scan paths and instruction retries, and a flip-flop that switches the scan path selection mode in the arithmetic processing unit 2. (hereinafter referred to as FF)
) 11, a scan path address register (hereinafter referred to as address register) 12 that stores a scan path address in the arithmetic processing unit 2, and a scan data register (hereinafter referred to as data register) 13 that stores scan data. We are prepared.

The arithmetic processing unit 2 executes scan-in, scan-out, and instruction retry under the control of the diagnostic control unit 1, and creates a scan path (hereinafter referred to as scan path I) in which register groups 3 in the device are connected in cascade. ) and the software register group 31- (hatched area in the figure), which requires a validity check when retrying an instruction, are connected in cascade (hereinafter referred to as scan path). A selector 4 is provided for selecting one of scan path 1 and scan path ■.

FIG. 2 is a block diagram showing the configuration of the arithmetic processing device 2 of FIG. 11. In the figure, register groups 3a to 3d in the arithmetic processing unit 2 are each connected in cascade to form a scan path (hereinafter referred to as scan path Ia-16), and software visible registers 7 in registers P43a to 3d
J31a, 31. b are connected in cascade to form a scan path (hereinafter referred to as scan path Ua), and software visible register groups 31 . c and 31d are each connected in cascade to form a scan path (hereinafter referred to as scan path nb).

The scan path select mode sent from the FF 11 of the diagnostic control device 1 is held in a scan path select mode register (hereinafter referred to as mode register) 6, and is output from the mode register 6 to selectors 4 and 5, respectively.

Further, the scan path address sent from the address register 12 of the diagnostic control device 1 is stored in the scan path address register (hereinafter referred to as address register) 7, and is output from the address register 7 to the selector 5. The selector 5 selects one of the scan paths Ia to Id and the scan path rlanb according to the scan path selection mode from the mode register 6, and supplies the scan path address to the selected scan path.

Furthermore, the scan data sent from the data register 13 of the diagnostic control device 1 is input to the selector 4, and the scan path Ia-16 and the scan path selected by the selector 4 according to the scan path selection mode from the mode register 6 are input. 1. a and IIb.

Here, in FIG. 2, only the register groups 3a to 3d and the software visible register groups 31a to 31d within the register groups 3a to 3d are shown, and other register groups and software visible register groups are not shown. Not yet.

The operation of an embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

The diagnostic control device 1 has its own diagnostic control software, and this diagnostic control software allows the arithmetic processing device 2 to
handles problems, etc.

Normally, the value of F F 1.1 of the diagnostic control device 1 is “0” (
・As a result, the scan path selection mode from F F 1-1 to selectors 4 and 5 in the arithmetic processing unit 2 also becomes "O", so the scan paths Ia to Id are selected in selectors 4 and 5, respectively. , scan in, and sometimes the scan path address of the address register 12 is set to the scan path address, and then the free money data of the data register 13 is scanned to the scan path Ia, -1d.

Also, at the time of scan out, the scan path Ta to I is scanned according to the scan path address of the address register 12.
The data of d is scanned out to the data register 13.

Now, while operating the arithmetic processing unit 2, there is a failure within the unit.
When executing an instruction retry in the arithmetic processing unit 2 under the control of the diagnostic control device 1, the validity of the contents of the software visible register group 313-31d in the arithmetic processing unit 2 is checked, and the contents are checked. It must be written back to the software visible registers n31a to 3]d.

At this time, the diagnostic control device 1 reads the contents of the software accessible register 31 a = 3 td in the arithmetic processing device 2, checks the validity of the contents, and writes back the contents. By setting the digit of 0) to "1" in the arithmetic processing unit 2, the scan path na,,I
Enable lb.

That is, by setting the scan path select l-=6-de of the FF 11 to "1", the selectors 4 and 5 select the scan paths Ua and Ilb, respectively, and apply them to the software visible register groups 31a to 31] and d. (Only 2 scans in and out.

The diagnostic control device 1 is a software visible lens star group 31
After checking the validity of the contents scanned out from a to 31d, the arithmetic processing unit 2 is reset to remove the cause of the failure of the arithmetic processing unit 2, and the contents whose validity has been checked are checked in the software. It writes back to the pull registers il 31a to 31d to cause the arithmetic processing unit 2 to retry the instruction.

As a result, when retrying the instruction of the arithmetic processing unit 2,
Since scan-in and scan-out are performed only for the software visible register groups 31a to 31d,
Software visible register group 31a-31. The 11 contents of the register group unrelated to d are not scanned out, and the instruction of the arithmetic processing unit 2 can be retried at high speed.

In this way, software visible register groups 31a to 31 . , d are connected in cascade to form scan paths Ta and Ilb to tINi.
-1 When retrying the instruction of the arithmetic processing unit 2, the diagnostic control device 1's F F] is configured to switch from the scan path Ta-1d to the scan paths Ila and IIb by the selector 4.5 according to the scan path selection mode from -1. By doing this, software visible registers 31a to 31d whose validity must be checked when retrying an instruction are
Since only the contents of the register can be scanned out, the contents of an unnecessary register group are not scanned out, and the execution of instruction retry can be sped up.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a group of registers whose validity needs to be confirmed at the time of retrying an instruction is connected in cascade among a plurality of registers in a device constituting a first scan path. By configuring two scan paths and selecting one of the first and second scan paths in response to an instruction signal from the diagnostic device, command retry can be speeded up. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of the arithmetic processing device shown in FIG. Explanation of symbols of main parts 1...Diagnostic control device 2...Arithmetic processing unit 3.3a to 3b...Register group 4.5...
... Selector 11 ... Flip-flop 12 ... Scan path address register 1 3 ... Scan data registers a to 31 b ... Software visible register group

Claims (1)

[Claims] (1) An information processing device configured by cascading each of a plurality of registers in the device and having a first scan path that can be freely scanned in and scanned out from a diagnostic device, wherein the information processing device a second scan path configured by cascading a group of registers whose validity needs to be confirmed during a trial; and one of the first and second scan paths in response to an instruction signal from the diagnostic device. 1. An information processing device comprising: a selection means for making a selection.