JPS60254331A - Trouble processing method of data processing system - Google Patents

Abstract

PURPOSE:To execute retry of a trouble by reserving the report of the trouble detected by an instruction supplying circuit part until the end of the execution of an instruction word which is being executed in an instruction executing circuit part, and at the end of the execution, reporting the trouble to a diagnozing device. CONSTITUTION:If an error is detected by a detector 211 and the output of the detector 211 is turned to the high level during the processing of an instruction C in the instruction supplying circuit 21, the high level output of the detector 211 is applied to an FF27 by an instruction end specifying pulse 2,300 appearing at the complete end of the execution of an instruction word A being executed in the instruction executing circuit 23, i.e. at the end of the execution of A3, to set up the FF27 and the output of the FF27 is applied to the diagnozing device 3 as the error information. Since the execution of the succeeding new instruction word B is not almost started, that the instruction word A is retriable is decided and retry is executed when the succeeding instruction word B is read out from a main storage 1 by the instruction supplying circuit 21.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a fault handling method in a data processing system, and particularly to a fault handling method in a data processing system having a diagnostic device that analyzes a fault state of a data processing device and executes a retry if possible. Regarding the method.

(Prior Art) Failure handling in this type of data processing system has conventionally been performed as shown below.

FIG. 1 is a block diagram showing a conventional example.

Instruction supply circuit 21' included in data processing device 2'
extracts instructions from the main memory 1' and forms a queue of instructions in the instruction buffer 22'.

The instruction execution circuit 23' receives instructions from the instruction buffer 722', executes the instructions sequentially, and stores the results in a software-visible register (software-visible register, 8VR) 232' or line 23.
00 to the main storage device 1'.

Now, in such an operation, if an error occurs in the data processing device 2', this error will be transmitted to the instruction supply circuit 21', the instruction buffer 22', and the instruction execution circuit 23.
Fault detectors 211', 2 provided in each of '
21' and 231', the output from the OR gate 24' is ORed, and the combined output sets the 7-rip prop 25', and as a result, the error report line 2500' An error report is made to the diagnostic device 3' via.

When the diagnostic device 3' receives this report, it sends the line 3001'.
An error log (failure information) collection request is issued to the data processing device 2' via.

Upon receiving this, the data processing device 2'
0' to the diagnostic device 3' (this transfer generally involves sequentially connecting necessary registers and flip-flops in the data processing device 2' to form a shift path, and diagnosing their contents. Shifting into device 3' is optional).

The diagnostic device 3' analyzes the error log transferred in this way, and if the result shows that a retry is possible, it issues an instruction to the data processing device 2' to retry via the 2-in 3002'. The above sequence is shown in FIG. Note that if retrying is not possible at this time, the system will go down.

Now, in such a failure handling system.

The criterion for determining whether the diagnostic device 3' can retry 6 is that the gator processing device 2'
The instruction currently being executed in the instruction execution circuit 23' has already been stored in the software visible register (SVR).
) 232' or the main memory 1' is judged based on whether or not the contents of the main memory 1' have been updated in the previous execution stages of this instruction.

That is, the currently executing instruction, which may contain an error, has already caused software visible registers (SVRs) to
) 232' or the main storage device 1', it is treated as if the update has already been done and cannot be retried, resulting in a system down.

On the other hand, if the currently executing instruction has not yet updated either the software visible register (SVR) 232' or the main memory 1', the new instruction is updated in the main memory 1'. A retry is commanded from the point read from 1'.

In this case, in the prior art, the occurrence of an error is detected only by the failure detection circuit 211' in the instruction supply circuit 21', so even if the currently executed instruction does not contain an error, for example, If the contents of the software-visible register (8VR) 232' or the main storage device 1' are updated by an instruction currently being executed, the system is brought down as a retry is not possible.

Therefore, even if, for example, a soft error occurs in the instruction supply circuit 21', which has a complicated configuration including a cache memory, etc., a retry will not necessarily be performed, and the probability of system failure will increase accordingly. This has the disadvantage of making it unnecessarily high.

(Objective of the Invention) The object of the present invention is to eliminate the above-mentioned conventional drawbacks, and to avoid unnecessary retry failures by simply adding hardware, thereby improving operating efficiency. An object of the present invention is to provide a failure handling method in a data processing system that improves the performance.

(Structure of the Invention) The method of the present invention is a data processing system equipped with a diagnostic device A that analyzes a failure state of a data processing device and causes the data processing device to perform a -C retry if possible. a fault detection means for separately detecting faults in the instruction execution circuit section and the instruction supply circuit section in the apparatus; and a fault reporting means that waits for the completion of the command being executed and then reports the fault to the diagnostic device.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.

This embodiment is a data processing system including a main storage device 1, a data processing device 2, and a diagnostic device fM3.

The data processing device 2 further includes an instruction supply circuit 21, an instruction buffer 22, an instruction execution circuit 23, an OR gate 24, a flip-flop 25, an AND gate 26, and a flip-flop 27.

Further, the reference supply circuit 21, 66 instruction buffer 22 and the instruction execution circuit 23 each have fault detectors 211, 221 and 231, respectively.

These fault detectors can be easily implemented as detectors that detect parity errors in instruction words processed in each circuit.

Further, the instruction execution circuit 'N123 includes a software-visible register (8VR) 232.

The operation of this embodiment is as follows.

An instruction supply circuit 21 in the data processing device 2 takes out an instruction from the main memory 1 and supplies it to an instruction buffer 22.

The instruction buffer 22 is a first-in, first-out buffer that stores supplied instructions in the form of a queue.

Every time the instruction execution circuit 23 finishes executing a new instruction, the instruction at the head of the queue is removed from the queue and supplied to the instruction execution circuit 23. In this way, the next instruction is executed by the execution circuit 23. and executed.

The execution result of the executed instruction is written to a software visible register (8VR) 232 or stored in the main memory 1 via line 2300.

Now, while the command words are being executed one after another, the failure detector 211 included in the command supply circuit 21
Suppose that detects an error. Then, the error detection flip-flop (not shown) included in the detector 211 is immediately set, and as a result, the line 2110 changes from the normal state θ" to 1", and thereafter maintains the state of "1". .

The output of this line 2110 is supplied to the input side of the flip-flop 270 via the AND gate 26.
An instruction end instruction pulse 2300 from No. 3 is supplied. This instruction end instruction pulse 2300 is transmitted to the instruction execution circuit 2
3, it is a logic "1" pulse that is output when execution of one instruction ends and before execution of the next instruction begins.

However, at some point in time, the fault detector 211 of the instruction supply circuit 21 detects the line 2- as described above, and as a result, the line 21
Suppose that 10 becomes 1''. At this point, when the instruction being executed in the instruction execution circuit 23 ends, the above-mentioned instruction end instruction pulse 2300 is output, and 1'' on the line 2110 passes through the AND gate 26 and is reset to 0'' in the normal state. Flip-flop 27
is set to 1" at the end of this command.

The output ``1'' of the flip 70 knob 27 is set via the OR gate 24 to the flip-flop 25k ``1'' which is normally reset to ii``o''.

As a result, the output of the flip-flop 25 is reported to the diagnostic device 3 via the error report line 2500 when one instruction is completed.

Upon receiving this report, the diagnostic device 3 immediately sends an error log collection request to the data processor 1 device 2 via line 3001 and outputs -C.

Upon receiving this request, the data processing device 2 immediately stops normal operation, connects the necessary registers and flip-flops in the data processing device 2 in series, and forms a shift bus.
These contents are sent to the diagnostic equipment f13 via line 2000.
shift in.

The diagnostic device 3 analyzes the error log transferred in this way and determines whether a retry is possible.

Now, as mentioned above, the criteria for determining whether this trial is possible is whether the software-visible register (8VR) 232 has already been updated by executing an instruction that may contain an error, or -C determination is made as to whether the contents of the main storage device 1 have been updated.

In the case of an error detected only by the fault detector 211 of the instruction supply circuit 21, as described above, wait until the instruction currently being executed in the instruction circuit 23 is completed, and then report the error. , to the diagnostic device 3. As a result of error log analysis, the diagnostic device 3 recognizes that this error report is a failure that occurred in the instruction supply circuit 21, and therefore there is no possibility that the currently completed instruction contains an error.

Furthermore, execution of the next instruction that may contain an error has hardly started yet, and the software-visible register (8VR) 232 is updated by this instruction.
It is clear that no situation has occurred in which the contents of the main storage device 1 have been updated. Therefore, in this case, the diagnostic device 3 can reliably command execution of a retry.

That is, in this case, the diagnostic device 3
, it instructs the data processing device 2 to read a new instruction word from the main storage device 1, starting from the instruction word next to the instruction word that has currently finished execution, and to retry the instruction word. .

In this way, according to this embodiment, when an error occurs in the instruction supply circuit 21, it is controlled so that a retry is reliably performed, and the system is not treated as a system failure as in the conventional example described above. Never. Moreover, the execution of the instruction that is being executed when the error is detected and is not likely to include an error is reliably continued until it is completed, and a retry is performed from the next instruction. In this way, the retry process is simplified and highly efficient.

Incidentally, FIG. 4 shows the above-mentioned operation as a time chart.

As shown in FIG. 4, the instruction supply circuit 21 supplies instruction words to the instruction buffer 22 in the order of, for example, A, B, C, D, E, . . . every syncycle. These instruction words are stored as a queue in the instruction buffer 22, and each time the instruction execution circuit 23 finishes executing one instruction, the first instruction word is removed from the queue and supplied to the circuit 23. is executed. The instruction word A is executed in three machine cycles in the instruction execution circuit 23, for example, t Id A+ , A2 , As (the machine cycles required to execute each instruction word vary depending on the instruction word).

Now, suppose that while the instruction supply circuit 21 is processing the instruction C, an error is detected by the detector 211, and the output (line 2110) of the detector 211 becomes '1''.

At this point, the output of the detector 211 is determined by the instruction end instruction pulse 2300 that appears when the execution of the instruction word A being executed by the instruction execution circuit 23 is completely completed. '1'' is added to flip-flop 27 to set it.
The output of 7 is applied to the flip-flop 25 to set it, and this output is reported to the diagnostic device 3 as an error report. It is clear from FIG. 4 that the executed instruction A is already being executed in the instruction execution circuit 23 when the error is detected in the instruction supply circuit 21 and is unrelated to the above-mentioned error. New next command word B
Since execution has hardly started, it is determined that retry is possible for the reason described above, and as a result, a retry is executed from the point where the instruction supply circuit 21 reads the next instruction word B from the main memory. Ru. Furthermore, the above-mentioned error detection flip-flop and flip-flop 27 included in the fault detector 211, as well as the flip-flop 25, are all reset to ``0'' before the retry begins, as shown in FIG.
You will be charged $ for the next error detected.

It should be noted that the above description shows a single mud row of the present invention, and the present invention is not limited to this embodiment.

For example, the flip-flop 27 shown in the above embodiment can be omitted.

(Effects of the Invention) As described above, according to the present invention, a fault detection step is provided to separately detect faults in the defense supply circuit section and the 61"i consideration circuit section in the data processing device. , a failure detected in the instruction supply circuit section is suspended from being reported until the execution of the instruction word currently being executed in the instruction execution circuit section is completed at that time,
The diagnostic device is made to report a failure after the completion of execution of the instruction word, thereby making it possible to ensure that a failure occurring in the instruction supply circuit section will be retried.

As a result of the above, it is possible to avoid situations where the system goes down unnecessarily, and to simplify and increase the efficiency of retry processing. The present invention is particularly effective when applied to a data processing system equipped with an instruction supply circuit having a complicated configuration including a cache memory.

4. Drawing J4! Figure 1 is a block diagram for explaining an example of the use of t. The block diagram shown and FIG. 4 are timing diagrams showing the operation of this embodiment.

In the figure, 1... King memory system, 2... Data processing device, 3... Diagnosis device, 21... Inquiry supply circuit, 22... ...Instruction buffer, 23...
...6δ instruction execution circuit, 24...OR gate,
25... Solitub flop, 26...°°
AND gate, 27...Solid flop, 2
11.221,231... Fault detector, 232
・・・・・・Software visible register (SVR)
).

Pile 1 time chita phantom, kuri, lit 2" diagnosis M1 cover 3'wa
2′ Figure, 3 Figure

Claims (1)

[Scope of Claim] A data processing system comprising a diagnostic device that analyzes a failure state of a data processing device and causes the data processing device to retry if possible, comprising: an instruction execution circuit section in the data processing device; fault detection means for separately detecting a fault in the instruction supply circuit and the instruction supply circuit; and if the fault detection means detects a fault in the instruction supply circuit, the instruction execution circuit waits for the end of the instruction being executed. A failure processing method in a data processing system, comprising: a failure reporting means for reporting a failure to the diagnostic device;