JPH0368046A - Memory access system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] In an information processing system, a memory access method for accessing a memory having a storage area larger than an address space held by a processing device is concerned. When accessing the common area of a specific block by address,
In order to prevent the creation of storage areas that are inaccessible to other blocks, the memory is divided into multiple blocks, each having a predetermined address area, and each block is divided into multiple sub-blocks. one or more holding means each holding a block number specifying a block and a subblock number specifying a subblock; a selection means for receiving the block number and sub-block number held by the selected holding means to the memory; The configuration is such that a desired storage area of the memory can be accessed using the block number and subblock number and the remainder of the address.

(Industrial Application Field) The present invention relates to a memory access method for accessing a memory having a storage area larger than an address space held by a processing device in an information processing system.

[Conventional technology]

FIG. 3 is a diagram showing an example of a conventional memory access method.

In FIG. 3, it is assumed that the memory 1 has a storage area twice as large as the address space held by a processing device (not shown).

In order to access a desired storage area in the memory 1,
The processing device divides the memory 1 into three blocks 11, 12 and 1, each having a storage area equal to the address space.
3, and assign block numbers b1, bt and b3 to each block 11, 12 and 13, respectively,
Before accessing any storage area in the memory 1, the block number is stored in the block register (BR) 21.
.

When and S are set, the block numbers S, b2 and S are transferred to the decoder (DE) via the converter (CNV) 22.
C) 3 and the corresponding activation signal else! is transmitted by the decoder (DEC) 3. Alternatively, the block 11, 12 or 13 corresponding to 8 after being converted to e3 is activated and made accessible.

Note that a part of the storage area 11 specified by the address space (hereinafter referred to as common address space) of block 11
0 (hereinafter referred to as common area 110) stores information unique to the information processing system.

The decoder (DEC) 23 monitors the address a output from the processing device, and when the common address ac is output, it controls the conversion unit (CNV) 22 and the decoder (
The block numbers S, b, and S output from the DEC 21 are all converted into an activation signal e.

As a result, if the common address space is output, the common area 110 of the block 11 will be accessed unconditionally.

As a result, the common address ac of blocks 12 and 13 is
The storage areas 120 and 130 corresponding to are inaccessible from the processing device.

[Problem to be solved by the invention]

As is clear from the above explanation, in a conventional memory access method, when the processing device transmits the common address a, 1 memory 1, the common area 1 of block 11
Since only block 10 can be accessed, storage areas 120 and 130 corresponding to the common address ac of other blocks 12 and 13 cannot be accessed.As the capacity of memory 1 increases and the number of blocks increases, There was a problem that the inaccessible storage area increased.

An object of the present invention is to prevent the creation of a storage area that cannot be accessed in other blocks even when a memory is divided into a plurality of blocks and a common area of a specific block is accessed using a common address. .

[Means to solve the problem] FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 1 is a memory.

11, . . . In are a plurality of blocks provided in the memory 1 according to the present invention.

111, . . . , nm are each block 11 according to the present invention.
,... This is a sub-block provided in 1n.

Reference numeral 200 is a holding means arranged in one or more stages according to the present invention.

300 is a selection means provided according to the present invention.

[Effect]

Each of the blocks 11 to 1n has a predetermined address area and is assigned a predetermined block number, and each sub-block 111, . . . 1. nm is also assigned a predetermined sub-block number S, respectively.

Each holding means 200 holds a designated block number b and sub-block number S, respectively.

When the selection means 300 receives an address a for the memory 1, the selection means 300 receives a predetermined part of the address a as a sub-block number S, and selects one holding means 200 from one or more holding means 200. , selected holding means 2
The block number S and sub-block number S held by 00 are applied to the memory 1.

The memory 1 can access a desired storage area using the block number S and sub-block number S applied from the selection means 300 and the remainder of the address a.

Therefore, by setting required block numbers and sub-block numbers in advance in the holding means, it becomes possible to access arbitrary blocks and sub-blocks in the memory, and it becomes possible to remove inaccessible storage areas.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a memory access method according to an embodiment of the present invention. Note that the same reference numerals refer to the same objects throughout the plan.

In FIG. 2, the memory 1 has a storage area twice as large as the address space held by a processing device (not shown), each having the same storage area as the address space, and each having a block number. It is divided into three blocks 11, 12 and 13 which are given b2 and b3,
Each block 11, 12, and 13 has the same storage area, and has subblock numbers s0 to S.
, four sets of sub-blocks 110s to 113 given
s, 120s to 123s and 130s to 133S
It is divided into

In addition, the sub-boots in each block 11, 12 and 13
Address a given to TsukullOs, 120s and 130s. The top two fingers are the sub-block number So (
For example, "00"), and subblocks 111S, 121
The upper two fingers of the address space assigned to s and 131s are the subblock number S+ (for example, roIJ), and the upper two fingers of the address bus 8 assigned to the subblocks 112S, 122S, and 132s are the subblock number s.
2 (for example "10"), and further sub-bu 07ri 113s,
The upper two fingers of the address bus 8 assigned to 123s and 133s are subblock numbers S= (for example, "11"
), and each of the three addresses acsa11 to as3 or less is an intra-subblock address a.

Further, in FIG. 2, the holding means 200 in FIG.
As, three sets of registers (REG) 51, 52 and 5
A decoder (DEC) 6 and gates 71, 72 and 73 are provided as the selection means 300 in FIG.

In FIG. 2, a processing device (not shown) includes sub-blocks llOs, 120s, 130S and ILI of memory 1.
s, the processing device first sends the address bus 8 assigned to the register (REG) 51 to the address bus 8, and also sends the block number b2 and the block number b2 specifying the block 12 to the data bus 9. Sends sub-block number s0 specifying sub-block 120S,
Furthermore, when a write signal W is sent to the write signal line 101, the decoder (DEC) 4 that has received the write signal W is activated.
The address bus I received via the address bus 8 is converted into a clock signal Ci and input to the register (R, EC) 51.

As a result, the register (REG) 51 accumulates the block number b2 and sub-block number S0 received via the data bus 9, and transmits them to the gate 71.

Next, the processing device sends a register (REG) to address bus 8.
52, the block number b3 specifying the block 13 and the subblock number So specifying the subblock 130s are sent to the data bus 9, and the write signal line 101 is also sent. When the signal W is sent, the decoder (DEC) 4 converts the address bus z received via the address bus 8 into a clock signal C2, inputs it to the register (REG) 52, and registers (R
EG) 52 is the block number bff and sub-block number S received via the data bus 9. is accumulated and transmitted to gate 72.

Furthermore, the processing device connects a register (REG) to the address bus 8.
53, the block number S specifying the block 11, and the subblock number S specifying the subblock 111S are sent to the data bus 9. When the write signal W is sent, the decoder (DEC) 4 converts the address bus 3 received via the address bus 8 into a clock signal C3, inputs it to the register (R, EC) 53, and registers (
R, EC) 53 stores the block number and sub-block number S1 received via the data bus 9,
The signal is transmitted to gate 73.

On the other hand, the gate 70 has a sub-block 11 of the block 11.
The block number b1 and sub-block number S0 specifying 0s (common area) are fixedly entered manually.

However, all of the gates 70 to 73 are currently set to a blocked state, and the block number, sub-block number S0, block number b2, sub-block number So, block number, and sub-block number are manually input. S. Also, the block number S and sub-block number S are not output.

In this state, when the processing device attempting to access the sub-block llOs sends the common address bus (C-5o +a-s) to the address bus 8, the processing device attempts to access the sub-block llOs.
The subblock number line 81, which transmits the upper two fingers corresponding to the subblock number S, transmits the subblock number S0 to the decoder (DEC) 6, and the two fingers corresponding to the remaining subblock addresses a-S. The intra-subblock address line 82 that transmits the following is an intra-subblock address a-3.
is transmitted to address register (AR) 2.

The decoder (DEC) 6, which is always activated, converts the sub-block number S0 received via the sub-block number line 81 into a gate signal g0, and transmits it to the gate 70.

Gate signal g. The game (DEC) 70 that has received this is set to a conductive state, transmits the fixedly input block number S to the decoder (DEC) 3 via the block number line (02), and also transmits the sub-block number S to the sub-block number S. Block number line 81
1 to the address register (AR) 2.

As a result, address register (AR) 2 contains gate 7.
The sub-block number S0 transmitted from 0 via the sub-block number line 81' and the intra-sub-block address a-s transmitted from the processing device via the intra-sub-block address line 82 are connected to a common address bus. and is transmitted to memory 1.

On the other hand, the decoder (DEC) 3 converts the block number S transmitted from the gate 70 via the block number line 102 into an activation signal e, and transmits it to the block 11.

As a result, the block 11 that has received the activation signal e from the decoder (DEC) 3 is activated, and the sub-block 110S (common area) corresponding to the common address bus received from the address register (AR) 2 can be accessed. Become.

Next, the processing device attempting to access the sub-block 120s specifies the block number b2 and the sub-block number.

. The sub-block number S corresponding to the register (REG) 51 in which the
When an address a with 2 fingers or less is sent to the address bus 8, the sub-block number line 81 of the address bus 8 transmits the sub-block number S1 to the decoder (DEC) 6, and the intra-sub-block address line 82 transmits the sub-block number S1 to the decoder (DEC) 6. The intra-subblock address a-S is transmitted to the address register (AR) 2.

A decoder (DEC) 6 sends a sub-block number S1 received via a sub-block number line 81 to a gate signal g.
and transmits it to the gate 71.

The gate 71 that has received the gate signal g1 is set to a conductive state, and the block number b2 inputted from the register (REG) 51 is sent to the decoder (
The sub-block number S0 is transmitted to the address register (A) via the sub-block number line 81".
R) 2.

As a result, address register (AR) 2 contains gate 7.
The sub-block number S0 transmitted from 1 through the sub-block number line 81' and the intra-sub-block address a-s transmitted from the processing device through the intra-sub-block address line 82 are address a, and is transmitted to memory l.

On the other hand, the decoder (DEC) 3 converts the block number b2 transmitted from the gate 71 via the block number line 102 into an activation signal e2, and transmits it to the block 12.

As a result, the block 12 that has received the activation signal e2 from the decoder (DEC) 3 is activated, and the sub-block 120S corresponding to the address ac received from the address register (AR) 2 can be accessed.

Next, the processing device attempting to access the sub-block 130S specifies the block number b3 and the sub-block number S. The sub-block number S2 corresponding to the register (REG) 52 in which the When sent, address bus 8
The sub-block number line 81 is the sub-block number S2.
is transmitted to the decoder (DEC) 6, and the intra-subblock address line 82 transmits the intra-subblock address a-S to the address register (AR) 2.

A decoder (DEC) 6 sends a sub-block number S2 received via a sub-block number line 81 to a gate signal gt.
and transmits it to the gate 72.

The gate 72 that has received the gate signal g2 is set to a conductive state, and the block number inputted from the register (REG) 52 is sent to the decoder (
The sub-block number S0 is transmitted to the address register (A) via the sub-block number line 811.
R) 2.

As a result, address register (AR) 2 contains gate 7.
The sub-block number S0 transmitted from 2 via the sub-block number line 81'' and the intra-sub-block address a-s transmitted from the processing device via the intra-sub-block address line 82 are used as the address ac. is set and transmitted to memory 1.

On the other hand, the decoder (DEC) 3 converts the block number b3 transmitted from the gate 72 via the block number line 102 into an activation signal e, and transmits it to the block 12.

As a result, the block 13 that has received the activation signal e3 from the decoder (DEC) 3 is activated, and the sub-block 130s corresponding to the address ac received from the address register (AR) 2 can be accessed.

Furthermore, the processing device attempting to access the sub-block 111s specifies the top two block numbers S specifying the sub-block 1lls and the sub-block number S corresponding to the register (REG) 53 in which the sub-block number S East is set. Then, when the address a which makes the sub-block address a-s in the sub-block 1lls to be accessed less than or equal to two fingers is sent to the address bus 8, the address bus 8
The sub-block number line 81 is the sub-block number S3.
is transmitted to the decoder (DEC) 6, and the intra-subblock address line 82 transmits the intra-subblock address a-S to the address register (AR) 2.

A decoder (DEC) 6 sends a sub-block number S3 received via a sub-block number line 81 to a gate signal g.
and transmits it to the gate 73.

The gate 73 that has received the gate signal g3 is set to a conductive state, transmits the block number input from the register (REG) 5'3 to the decoder (DEC) 3 via the block number line 102, and also Block number S is sent to the address register (
AR) 2.

As a result, address register (AR) 2 contains gate 7.
The sub-block number S transmitted from No. 3 via the sub-block number line 811 and the intra-sub-block address a-s transmitted from the processing device via the intra-sub-block address line 82 are used as address a0. is set and transmitted to memory 1.

On the other hand, the decoder (DEC) 3 converts the block number S transmitted from the gate 73 via the block number line 102 into an activation signal el, and transmits it to the block 11.

As a result, the block 11 that has received the activation signal el from the decoder (DEC) 3 is activated, and the sub-block 130s corresponding to the address bus received from the address register (AR) 2 can be accessed.

As is clear from the above description, according to this embodiment, any subblocks 111s to 113s, 12O8 to 123s, 1
After setting block numbers S to s3 specifying 30s to 133S and sub-block numbers S0 to s3 in registers (REG) 51 to 53 in advance, each register (R
EG) Any subblock 111S to 113S, 120 by sending address a whose upper two fingers are subblock numbers s to S corresponding to 51 to 53.
s to 123s and 130s to 133S can be accessed. Note that the sub-block 110s, which is a common area, can be accessed without storing anything in the registers (REG) 51 to 53 by sending out a common address bus as before.

Note that FIG. 2 is merely one embodiment of the present invention, and for example, the configuration of the memory 1 is not limited to that shown in the figure, and many other modifications may be considered, but in any case However, the effect of the present invention remains unchanged.

Furthermore, the holding means 200 and the selection means 300 are not limited to the illustrated three sets of registers (REG) 51 to 53, the decoder (DEC) 6, and the four sets of gates 70 to 73, and may include many other sets of gates 70 to 73. Although variations are considered, the effects of the present invention do not change in any case.

〔Effect of the invention〕

As described above, according to the present invention, by setting the required block number and sub-block number in the holding means in advance, it becomes possible to access any block and sub-block in the memory, and eliminate inaccessible storage areas. It becomes possible.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a memory access method according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of a conventional memory access method. In the figure, 1 is memory, 2 is address register (AR
), 3.4.6 and 23 are decoders (DEC), 8 is an address bus, 9 is a data bus, 11 to 13 are blocks, 21 is a block register (BR), and 22 is a conversion unit (
CNV), 51 to 53 are registers (REG), 7
0 to 73 are gates, 81 and 81° are subblock number lines, 82 is an intra-subblock address line, 101 is a write signal line, 102 is a block number line, 110 is a common area, 110S to 113s, 120S to 123s, 13
0s to 133s are sub-blocks.

Claims (1)

[Claims] A memory (1) is divided into a plurality of blocks (11,..., 1n) each having a predetermined address area, and each block (11,..., 1n) is divided into a plurality of blocks (11,..., 1n) each having a predetermined address area. A block number (b) that is divided into a plurality of sub-blocks (111, . . . , 1 nm) and specifies each of the blocks (11, . . . , 1n);
Sub-block number (s
); and when an address (a) for the memory (1) is received, a predetermined part of the address (a) is set as the sub-block number (s); one holding means (200) from among the one or more holding means (200), and the block number (b) and sub-block number (s) held by the selected holding means (200). ) to the memory (1);
A desired storage area of the memory (1) can be accessed by the block number (b) and the sub-block number (s) applied from the selection means (300) and the remainder of the address (a). A memory access method characterized by: