JPS6350141A - Data exchanging device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data exchange device which makes it possible to access a wider space through a fixed address space for data exchange. .

2. Description of the Related Art FIG. 2 is a block diagram of a data exchange device comprising a plurality of distributed processing systems that share memory for data exchange. In FIG. 2, numeral 4 represents a distributed processing system including a central processing unit, and there are a plurality of distributed processing systems. Reference numeral 5 denotes a memory for data exchange, and access to this memory from the distributed processing system 4 is performed via a system bus 6.

FIG. 3 shows how the address space for data exchange allocated on the entire address space of the central processing unit is related to the memory for actual data exchange from the perspective of each distributed processing system 4. It is.

Normally, the address of the data exchange memory 5 is allocated to a part of the total address space when viewed from the central processing unit of the distributed processing system 4. Therefore, in order to access the memory for data exchange, the central processing unit must access the address space allocated for data exchange. That is, an address space for data exchange is allocated on the entire address space 41 of the central processing unit in the distributed processing system 4, and when this area (shaded area) is accessed, the memory for data exchange is accessed.

Conventionally, the space allocated for this data exchange was the memory itself for data exchange.

Problems to be Solved by the Invention In such conventional circuits, as the memory for data exchange increases, the number of addresses for data exchange increases in the total address space of the central processing unit, resulting in a distributed processing system. The disadvantage was that the address space that could be used was limited.

SUMMARY OF THE INVENTION An object of the present invention is to provide a device that has a simple configuration and provides a memory space for wide data exchange without taking up a large address space of a central processing unit.

Means for Solving the Problems In order to solve the above problems, the present invention assumes that memory access for data exchange is performed in units of a fixed amount, and that fixed amount of address space is used as the entire address space of the central processing unit. When the address space for data exchange is accessed, the address signal of the central processing unit is converted into a memory address signal for data exchange.

According to the above-described configuration, when the address space for data exchange is accessed, part of the address of the central processing unit is replaced with a preset value.
By changing this preset value, it becomes possible to access any wide area.

Embodiment FIG. 1 is a block diagram showing an embodiment of the data exchanger of the present invention. In the figure, 1 is an address decoding circuit, which has an input terminal 11 and an output terminal 12.The address bus of the central processing unit is input to the input terminal 11, and the address space for data exchange is accessed. It detects and outputs a detection signal to the output terminal 12. 2 is a memory circuit, and has input terminals 21 . Output terminal 22. Memory control terminal 2
3, the signal input to the input terminal 21 is output to the output terminal 22 by the storage control signal input to the storage control terminal 23.
The output state is maintained until the storage control signal is input again. 3 is a data selection circuit, which has input terminals 31, 32, output terminals 33. i! It has a selection terminal 34, and depending on the state of the selection terminal 34, the input terminal 31 or 3
2 to the output terminal 33.

Here, using a central processing unit with a 20-bit address space, 64 addresses from 80000 to 8FFFF are used.
A detailed explanation will be given by taking as an example a system in which bytes are used as address space for data exchange, and the memory for data exchange is accessed in units of 64 bytes (16 bits).

The upper four vias of the address signal of the central processing unit are input to the input terminal 11 of the address decoding circuit 1, and when the value is "8", the output terminal 12 is set to . Memory circuit 2
holds 4-bit data and can be set by the central processing unit. The data selection circuit 3 inputs the upper 4 bits of the address signal of the central processing unit to the input terminal 31 and the output 4 bits of the memory circuit 2 to the input terminal 32. When the selection terminal 34 is "1", the data is input to the input terminal 32. The input signal is output to the output terminal 32, and the signal input to the input terminal 31 at "θ' is output to the output terminal 33. That is, by setting data 'n' in the memory circuit 2, address 8x
When xxx (x is any 4-bit value) is accessed, the address is changed to nxxxx. The lower 16 bits of the address of the central processing unit are used as is. Therefore, n
By changing , it is possible to access a 1 megabyte address space in 64 byte units. If the upper 4 bits of the address of the central processing unit are other than "8", such conversion is not performed.

Effects of the Invention As described above, according to the present invention, a large space for data exchange can be secured with an extremely simple circuit configuration, and the present invention is practical and extremely useful.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data exchange device according to an embodiment of the present invention, FIG. 2 is a block diagram of a data exchange device comprising a plurality of distributed processing systems, and FIG. 3 is an address translation unit in a conventional data exchange device. FIG. 1...Address decoding circuit, 2...
Memory circuit, 3...Data selection circuit, 4...
... Distributed processing system, 5 ... Memory for data exchange, 6 ... System bus, 11 ...
...Input terminal, 12...Output terminal, 21...
...Input terminal, 22...Output terminal, 23...
...Storage control terminal, 31.32...Input terminal, 33...Output terminal, 34...Selection terminal, 41...Address space. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 1 Figure 2 Δ

Claims (1)

[Claims] This system allocates an address space for data exchange on the address space of a central processing unit, and includes a storage circuit that can be set by the central processing unit, and an address decoding circuit that detects access to the address space for data exchange. , a data select circuit that uses a part of the address signal of the central processing unit and the output signal of the storage circuit as input signals, and uses the output signal of the address decoding circuit as a selection signal to switch the output signal, and has an address signal for data conversion. A data exchange device comprising means for changing the address signal of a central processing unit when accessing space.