JPH0368418B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an interrupt control device that outputs an interrupt request signal to a stored program controlled data processing device.

[Prior art]

When an application system is designed using an interrupt function, situations often occur in which multiple interrupts occur simultaneously, or another interrupt occurs during interrupt processing. Under such an environment, the problem is which of the plurality of interrupt requests should be prioritized, and this is usually dealt with by associating priorities with the interrupt requests. However, in an application system in which priorities are associated with interrupt requests, if it takes a long time to process an interrupt request with a high priority, the interrupt requests with a lower priority will be kept waiting during this time and will not be able to respond to the interrupt request. This may cause an overrun. To avoid such a situation, lower the priority of the high priority, process the low priority interrupt first while it is waiting, and then
It is necessary to process the downgraded high-priority interrupt.

Conventionally, the above-mentioned operations have been processed using a hardware function that can arbitrarily set the priority order of interrupt requests. Therefore, a register for holding the priority of the interrupt request currently being serviced,
This requires a register to specify the priority for each interrupt request and a circuit to compare the priority specified for each interrupt request with the priority of the interrupt request currently being serviced, which increases the hardware burden. It has the drawback of becoming extremely large and increasing the cost of the applied system.

[Purpose of the invention]

An object of the present invention is to provide an interrupt control device that can easily realize variable priority operations by eliminating the above-mentioned drawbacks.

[Structure of the invention]

The interrupt control device of the present invention is an interrupt control device that outputs an interrupt request signal to a data processing device under stored program control, and the interrupt control device outputs a plurality of interrupt requests Si (i is a positive value from 1 to n) based on the execution of a specific instruction. a first interrupt request generating section that generates a first interrupt request generating section (an integer of The priorities of the interrupt requests Si and Hi from the second interrupt request generating section which generates a positive integer) and the first and second interrupt request generating sections are respectively set as sj and hj (j is from 1 to (n- (a positive integer up to 1), hj is given high priority, and the following sj, k (j + 1), s (j + 1) are determined to have low priority in that order, and the input interrupt request is
a priority determination unit that selects the one with the highest priority among Si and Hi and generates the interrupt request signal;
dividing a process based on a specific operation factor into first and second processes, generating the specific interrupt factor having a predetermined priority in response to the second process, and A priority control means includes a program having a low priority and arranged with an instruction that is executed after execution of the second process and corresponds to an interrupt request for executing the first process.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

This embodiment is an interrupt control device that outputs an interrupt request signal to a data processing device under stored program control, and generates a plurality of interrupt requests Si (i is a positive integer from 1 to n) based on the execution of a specific instruction.
A software interrupt request generation unit 1 as a first interrupt request generation unit that generates the interrupt request, and multiple interrupt requests other than interrupt requests generated by the software interrupt request generation unit 1 based on a specific interrupt factor.
Interrupts generated from the hardware interrupt request generation unit 3 as a second interrupt request generation unit that generates Hi (i is a positive integer from 1 to n) and the software and hardware interrupt request generation units 1 and 3. When the priorities of requests Si and Hi are respectively sj and hj (j is a positive integer from 1 to (n-1)), the following sj, k (j + 1), s (j + 1) with hj as high priority are given.
The input interrupt request is determined to have low priority in the order of
A priority determination unit 6 selects the highest priority among Si and Hi and generates an interrupt request signal, and divides processing based on a specific operation factor into first and second processing, and Generates a specific interrupt factor with a predetermined priority in response to the process, and has a lower priority than the specific interrupt factor, and is executed after the second process is executed and serves as an interrupt request for executing the first process. A data processing device (not shown) as a priority control means including a program in which corresponding instructions are arranged
, a software interrupt request storage section 2, a hardware interrupt request storage section 4, and an interrupt request control section 5. Note that 7 is an interrupt reception unit.

This embodiment handles interrupt requests caused by execution of software interrupt instructions a, b, and c as programmed interrupt requests Si, and handles interrupt requests based on hardware factors as interrupt requests Hi other than the interrupt requests Si. This is an interrupt control device that handles interrupt requests a, b, and c.

The software interrupt request generation unit 1 generates a software interrupt request signal 11 which becomes high level upon execution of a software interrupt instruction a, a software interrupt request signal 12 which attains a high level upon execution of a software interrupt instruction b, and a software interrupt request signal 12 which attains a high level upon execution of a software interrupt instruction b. Upon execution of the interrupt instruction c, a software interrupt request signal 13 that becomes high level is generated and output to the software interrupt request storage section 2.

The software interrupt request storage unit 2 detects that the software interrupt request signals 11, 12, and 13 have become high level, and stores flip-flops (hereinafter referred to as F/Fs) associated with each interrupt request.
That's what it means. ). 21, 22, and 23 are software interrupt request storage signals; signal 21 detects that the software interrupt request signal 11 becomes high level, and signal 22 detects that the software interrupt request signal 12 becomes high level. Upon detecting this, the signal 23 becomes high level upon detecting that the software interrupt request signal 13 has become high level.

The hardware interrupt request generation unit 3 generates an interrupt request based on external input to the data processing device, hardware factors such as a timer connected to the data processing device, and the hardware interrupt request a.
Hardware interrupt request signal 31 that becomes high level when a hardware interrupt request b occurs.
generates a hardware interrupt request signal 32 that becomes high level when a hardware interrupt request c occurs, and a hardware interrupt request signal 33 that becomes high level when a hardware interrupt request c occurs, and outputs them to the hardware interrupt request storage section 4. do.

The hardware interrupt request storage unit 4 detects that the hardware interrupt request signals 31, 32, and 33 have become high level, and stores them in the F/Fs associated with each interrupt request. 41, 42
and 43 are hardware interrupt request storage signals;
The signal 41 detects that the hardware interrupt request signal 31 becomes high level, the signal 42 detects that the hardware interrupt request signal 32 becomes high level, and the signal 43 detects the hardware interrupt request signal. 33 becomes high level, and each becomes high level.

The interrupt request control unit 5 enables all interrupts, including software interrupts and hardware interrupts.
It enables and disables interrupts for each interrupt request, and the software interrupt request storage unit 2
and interrupt request storage signals 21, 22, 23, 41, 42, from the hardware interrupt request storage section 4,
43 is connected. Outputs 51, 52, 53, 54, 55, and 56 of the interrupt request control unit 5 are enabled interrupt request signals that become high level when an interrupt request occurs and the interrupt is enabled, and 51 is a software interrupt instruction. Interrupt request by a, 5
2 is an interrupt request by software interrupt instruction b, 53 is an interrupt request by software interrupt instruction c, 54 is hardware interrupt request a, 55
56 corresponds to hardware interrupt request b, and 56 corresponds to hardware interrupt request c, respectively.

The priority determination unit 6 receives permission interrupt request signals 51, 52, and 52 output from the interrupt request control unit 5.
Among the interrupt requests 53, 54, 55, and 56, the interrupt request with the highest priority level is selected. Outputs 61, 62, 63,
64, 65, and 66 are priority determination signals in which only the output corresponding to the highest priority interrupt request becomes high level; 61 is an interrupt request by software interrupt instruction a, and 62 is an interrupt by software interrupt instruction b. 63 corresponds to an interrupt request by a software interrupt instruction c, 64 corresponds to a hardware interrupt request a, 65 corresponds to a hardware interrupt request b, and 66 corresponds to a hardware interrupt request c. Hardware interrupt request a has the highest priority, followed by software interrupt request a.
interrupt request by, hardware interrupt request b,
The order is interrupt request by software interrupt instruction b, hardware interrupt request c, and interrupt request by software interrupt instruction c, and cannot be changed.

The interrupt acceptance unit 7 sends the interrupt request determined to have the highest priority by the priority determination unit 6 to the CPU.
Let me know. Priority order determination signals 61, 62, 63, 64, 65, and 66 from the priority order determination section 6 are connected, and a processing interruption request signal 71 is output to the CPU.

FIG. 2 is a partial detailed circuit diagram of the embodiment shown in FIG. The logic circuit configuration is shown.

Next, the operation of this embodiment will be explained with reference to FIG.

In the hardware interrupt request storage unit 4, 81 detects that the hardware interrupt request signal 31 becomes high level due to the generation of hardware interrupt request a, and 82 detects that the hardware interrupt request signal 31 becomes high level due to the generation of hardware interrupt request b. A hardware interrupt request signal 83 is set upon detecting that the request signal 32 becomes high level, and detecting that the hardware interrupt request signal 33 becomes high level due to the generation of hardware interrupt request c. It is F/F. In the software interrupt request storage unit 2, 84 detects that the software interrupt request signal 11 becomes high level by executing the software interrupt instruction a, and 85 detects that the software interrupt request signal 11 becomes high level by executing the software interrupt instruction b. Upon detecting that the request signal 12 has become high level, 86 detects that the software interrupt request signal 13 has become high level by executing the software interrupt instruction c, and the software interrupt signal 86 is set. This is a request F/F.

In the interrupt request control unit 5, 91, 92, and 93 are hardware interrupt request enable F/Fs that permit each hardware interrupt request, and 93 is a hardware interrupt request enable F/F that allows the hardware interrupt request a to be set to the hardware interrupt request F/F 81. 92 is an F/F that allows the hardware interrupt request b that sets the hardware interrupt request F/F 82, and 91 is an F/F that allows the hardware interrupt request c that sets the hardware interrupt request F/F 83. It is. Hardware interrupt request permission F/F91,9
2 and 93 can be set and reset by an instruction, and when set, the corresponding hardware interrupt request is enabled.

94, 95, and 96 are software interrupt request enable F/Fs that permit each software interrupt request.
So, F/F94 is software interrupt request F/F
The software interrupt instruction a that sets 84
The F/F 95 allows an interrupt request by executing the software interrupt instruction b that sets the software interrupt request F/F 85, and the F/F 96 allows the interrupt request by executing the software interrupt request F/F 86. These are F/Fs that respectively permit interrupt requests caused by execution of the software interrupt instruction c to be set. Software interrupt request permission F/Fs 94, 95, and 96 can be set and reset by a command, and when set, the corresponding software interrupt request is permitted.

Reference numeral 103 denotes an interrupt enable F/F that controls enabling and disabling of all interrupts, and is set by executing an interrupt enable instruction and reset by executing an interrupt disable instruction. When the interrupt enable F/F 103 is reset, all hardware and software interrupt requests are prohibited.

97, 98, 99, 100, 101, and 102 are AND circuits, and one input terminal of each AND circuit is commonly connected to the output of the interrupt permission F/F 103. The input of the AND circuit 97 is further connected to the output of the hardware interrupt request enable F/F 93 and the output of the hardware interrupt request F/F 81, and the input of the AND circuit 98 is the output of the hardware interrupt request enable F/F 92 and the output of the hardware interrupt request F/F 81. The output of the hardware interrupt request F/F 82 is input to the AND circuit 99, and the output of the hardware interrupt request permission F/F 91 and the output of the hardware interrupt request F/F 83 are input to the AND circuit 99.
each connected. Also, AND circuit 100
Input software interrupt request enable F/F9
4 output and software interrupt request F/F84
The input of the AND circuit 101 is the output of the software interrupt request permission F/F 95 and the output of the software interrupt request permission F/F 85, and the input of the AND circuit 102 is the output of the software interrupt request permission F/F 96. The output and the output of the software interrupt request F/F 86 are connected respectively.
AND circuit 97, 98, 99, 100, 101,
The output of 102 is the permission interrupt request signal 54, 55,
56, 51, 52, 53, respectively, and each AND circuit 97, 98, 99, 100, 101, 1
Only when all inputs of 02 are at high level, each corresponding output becomes high level.

In other words, regardless of whether it is a hardware interrupt or a software interrupt, an interrupt request is processed by the priority determination unit 6.
In order to propagate the permission interrupt request signal to the CPU and request interrupt processing, an interrupt request is generated, the interrupt request is stored, and the corresponding interrupt request permission F/F and interrupt permission F/F 103 are set. The condition is that the

In the priority order determination unit 6, 116, 117, 11
8, 119, 120 are AND circuits, 111, 11
2, 113, 114, and 115 are inverter circuits. The input of the inverter circuit 111 is the output of the AND circuit 97, the input of the inverter circuit 112 is the output of the AND circuit 100, and the input of the inverter circuit 112 is the output of the AND circuit 100.
The output of the AND circuit 98 is connected to the input of the inverter circuit 114, the output of the AND circuit 101 is connected to the input of the inverter circuit 115, and the output of the AND circuit 99 is connected to the input of the inverter circuit 115. The output of the inverter circuit 111 and the output of the AND circuit 100 are input to the input of the AND circuit 118.
The outputs of the inverter circuits 111 and 112 and the output of the AND circuit 98 are input to the AND circuit 11.
Inverter circuits 111, 112, 1 are connected to the input of 9.
13 and the output of the AND circuit 101, and the input of the AND circuit 117 is the inverter circuit 111,
Outputs of 112, 113, 114 and AND circuit 9
The output of inverter circuits 111, 112, 113, 114 and the output of AND circuit 102 are connected to the input of AND circuit 120, respectively. And AND circuits 116, 117, 1
Priority determination signals 65, 66, 61, 62, and 63 are output from 18, 119, and 120, respectively. Each of the priority determination signals 61 to 66 is connected to an interrupt reception section, and the priority determination signal 64
becomes high level unconditionally when the output of the AND circuit 97 becomes high level, and the priority determination signal 61
becomes high level when the output of AND circuit 97 is low level and the output of AND circuit 100 is high level. Further, the priority determination signal 65 becomes high level when the outputs of the AND circuits 97 and 100 are low level and the output of the AND circuit 98 is high level, and the priority determination signal 62 becomes high level when the outputs of the AND circuits 97, 100, and 98 are high level. When the signal is at a low level and the AND circuit 101 is at a high level, it becomes a high level. Further, the priority order determination signal 66 becomes high level when AND circuits 97, 100, 98, and 101 become high level. Further, the priority determination signal 66 is outputted to AND circuits 97, 100, 9.
8 and 101 are low level and the AND circuit 99 is high level, the priority determination signal 63 becomes high level, and the AND circuit 97, 100,
When the outputs of 98, 101 and 99 are at low level and the output of AND circuit 102 is at high level, it becomes high level.

That is, the priority determination unit 6 receives the permission interrupt request signals 54, 55, 56, which are the outputs of the AND circuits 97, 98, 99, 100, 101, and
Regarding interrupt requests with 51, 52, and 53 at high level, hardware interrupt request a has the highest priority, and the following are interrupt requests by software interrupt instruction a, hardware interrupt request b, interrupt requests by software interrupt instruction b, The priority is set in the order of hardware interrupt request c and interrupt request by software interrupt instruction c, and the priority corresponds to the enable interrupt request signal with the highest priority among the enable interrupt request signals that are at high level. Set only the discrimination signal to high level.

Next, as an example, hardware interrupt request F/F
81 is a hardware interrupt request F/F82 is a hardware interrupt request F/F due to a timer interrupt.
F83 is an F/F that is set by a serial data reception interrupt, and software interrupt request F/F84 is a software interrupt instruction a, software interrupt request F/F85 is a software interrupt instruction b, and a software interrupt. The operation of this embodiment will be described assuming that the request F/F 86 is an F/F that is set by executing the software interrupt instruction c.

The priority determination unit 6 determines the key input interrupt from the CRT terminal as the highest priority, and the following interrupts are determined by software interrupt instruction a, timer interrupt, software interrupt instruction b, serial interrupt, and software interrupt. The determination is made in the order of the interrupts caused by the software interrupt instruction c. When a key input interrupt occurs from the CRT terminal, the hardware interrupt request signal 31 becomes high level, and the hardware interrupt request F/F 81
is set. At that time, hardware interrupt request permission F/F93 or interrupt permission F/F10
3 is reset, the output of the AND circuit 97 becomes low level and the interrupt request is not propagated. However, if the interrupt request enable F/F 93 and the interrupt enable F/F 103 are set, the output of the AND circuit 97 becomes low level. The signal becomes high level, and an interrupt request is transmitted to the priority determining unit 6 as a permission interrupt request signal 54.

Similarly, interrupt requests are made by other timer interrupts, serial data reception interrupts, and software interrupt instructions a, b, and c, and the corresponding hardware or software interrupt request permission F/Fs 91 and 9 are issued.
2, 93, 94, 95, 96 and interrupt permission F/
An interrupt request is transmitted to the priority determination section 6 only when F103 is set.

Here, hardware interrupt request enable F/F9
1, 92, 93, software interrupt request permission F/F94, 95, 96 and interrupt permission F/F1
03 is set, when a key input interrupt from the CRT terminal occurs, the output of the AND circuit 97, that is, the enable interrupt request signal 54
is at a high level. Therefore, the priority determination unit 6
The output of the inverter circuit 111 becomes low level, and the AND circuits 116, 117, 118, 11
9,120 output, that is, the priority determination signal 6
5, 66, 61, 62, and 63 are at low level. That is, when a key input interrupt occurs, only the priority determination signal 64 among the priority determination signals becomes high level. Priority determination signals 61 to 66
In the interrupt receiving unit 7 connected to the key input interrupt, the key input interrupt is recognized by the CPU in order to request the CPU to process the interrupt request corresponding to the high level signal among the priority determination signals.
Key input interrupt processing is started.

In this case, even if other timer interrupts, serial data reception interrupts, or interrupts due to the execution of software interrupt instructions a, b, and c have occurred, the key input interrupt is accepted as the highest priority interrupt request. Furthermore, since the key input interrupt processing has the highest priority, no interrupts are accepted during the key input interrupt processing.

Therefore, in the case of a program that requires a long time to process activated by a key input interrupt, the priority of the interrupt processing program should be lowered by the following operation in order to avoid ignoring timer interrupts and serial data reception interrupts. First, the program started by a key input interrupt is divided into a high priority processing program such as reading key input data, and a low priority processing program such as interpreting other input data, and the former is The latter is placed at the address of the key input interrupt processing routine, which is the original hardware interrupt, and the latter is placed at the address of the interrupt processing routine activated by the execution of the software interrupt instruction c, thereby positioning it as an independent interrupt processing. Further, a software interrupt instruction c is placed at the end of a high priority processing program, and a program is created so that a return instruction to the main routine is executed after setting the software interrupt request F/F 86.

Next, the operation of interrupt processing when programmed in this way will be explained. When a key input interrupt occurs, the process branches to the key input interrupt processing routine.
When high priority processing is completed, software interrupt instruction c is executed and software interrupt request F/
Set F86 and return to the main routine. Upon returning to the main routine, the hardware interrupt request F/F 81 is reset, so that lower priority interrupt requests can be accepted. In other words, timer interrupt requests,
If a serial data reception interrupt occurs and the corresponding hardware interrupt request F/F is set, the corresponding interrupt processing is performed. At this time,
Although the software interrupt request F/F 86 is set, the interrupt is not accepted because its priority is lower than that of a timer interrupt or a serial data reception interrupt. When the timer interrupt processing and serial data reception interrupt processing are completed and the process returns to the main routine again, the corresponding hardware interrupt request F/F is reset, so the interrupt request due to the execution of software interrupt instruction c is accepted, and the key The remaining input processing programs with low priority are executed, and all processes started by key input interrupts are terminated.

In other words, the priority of the process started by a key input interrupt is lowered after the high-priority process is finished, and after the timer interrupt or serial data reception interrupt process that has been waiting is performed, the remaining high-priority processes are This means that you have performed an operation that was not possible.

Also, if you want to accept only timer interrupts after high-priority processing in the key input interrupt processing routine has finished, use software interrupt command b.
If you return after executing , the interrupt request by software interrupt instruction b has a higher priority than the serial data reception interrupt, so the serial data reception interrupt will not be accepted until the processing started by software interrupt instruction b ends. First, a desired interrupt processing operation can be performed.

Furthermore, by executing a software interrupt instruction with a high priority, it is possible to raise the priority of interrupt processing.

〔Effect of the invention〕

As explained above in detail, the interrupt control device of the present invention has the above configuration, so it can generate a predetermined programmed interrupt request, determine its priority, and perform control, and handle interrupt processing. This has the effect that it is possible to easily perform variable priority processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a partially detailed circuit diagram. 1...Software interrupt request generation section, 2...
Software interrupt request storage unit, 3...Hardware interrupt request generation unit, 4...Hardware interrupt request storage unit, 5...Interrupt request control unit, 6...
Priority determination unit, 11-13...Software interrupt request signal, 21-23...Software interrupt request storage signal, 31-33...Hardware interrupt request signal, 41-43...Hardware interrupt Interrupt request storage signal, 51 to 56... Permission interrupt request signal, 61
~66...Priority determination signal, 71...Processing interruption request signal, 81-83...Hardware interrupt request flip-flop, 84-86...Software interrupt request flip-flop, 91-93...
Hardware interrupt request enable flip-flop,
94-96...Software interrupt request enable flip-flop, 103...Interrupt enable flip-flop, 97-102...AND circuit, 111-
115...Inverter circuit, 116-120...
AND circuit.

[Claims]

1. In an information processing system including a garbage collector and in which a memory space is divided for each data type, a memory scanning means for scanning a memory according to start address and end address data in the memory of a data type, and the memory scanning means means for counting the amount of active cells of each data type determined by the memory scanning means, means for counting the amount of garbage cells determined by the memory scanning means, and counting results of each and each past cell amount. means for predicting the future required cell amount for each data type from the actual usage value; means for determining the memory size for each data type from the predicted cell amount for each data type and the overall memory size; A memory capacity control method characterized by providing means for moving data according to the data.