JPH0369075B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a logic waveform generation circuit for generating various logic waveforms used in logic circuit tests, etc. The present invention also relates to a logic waveform generation circuit suitable for generating RTO waveforms at accurate timing.

[Background of the invention]

When testing a logic circuit, it is necessary to apply various logic waveforms such as NRZ waveform, RZ waveform, RTO waveform, and EOR waveform to the logic circuit under test. Also,
When the logic circuit under test is a microprocessor, etc., there are some that output a response waveform several cycles after applying the test waveform, and in order to perform an efficient test, multiple RZ waveforms or multiple RZ waveforms or
It is necessary to generate and apply an RTO waveform to advance the circuit under test by a few cycles.

FIG. 1 is a circuit diagram of an example of a conventional logic waveform generation circuit.

In this circuit, multiple
The case of generating an RZ waveform or RTO waveform (multi-clock mode) and the case of generating a normal logic waveform (normal mode) will be explained in detail.

In normal mode, D flip-flop 1a
The data input 12a and clock input 13a of
As shown in FIG. 2, which is a timing chart of the circuit of FIG. 1 in the normal mode, logic data A for controlling the logic waveform and timing clock B are supplied. Further, a second clock C (FIG. 2) is supplied to the clock input 14a, and various logic waveforms are generated by the logic elements 1a to 5a.
A desired waveform is selectively outputted to the polarity control gate 11a by the output waveform selection circuit 22a, and a logical waveform is obtained at the output 20a.

If you want to invert the polarity of the output waveform, use terminal 1.
The polarity control signal given to 9a may be set to "1".

The NRZ waveform is obtained at the output 21a of the D flip-flop 1a by supplying the aforementioned logic data A and clock B to the D flip-flop 1a. The NRZ waveform obtained at the output 21a of the D flip-flop 1a is shown as waveform D in FIG. In addition, when outputting this NRZ waveform, "1" is given to the output selection signal 16a and the AND gate 7a
By opening , the output 20a is obtained.

The RZ waveform is the output 2 of the D flip-flop 1a.
The NRZ waveform obtained at 1a is applied to the second clock C (second
), an RZ waveform shown as waveform E in FIG. 2 can be obtained. When outputting the RZ waveform, "1" is given to the output selection signal 17a to open the AND gate 8a.

The RTO waveform can be obtained by inverting the second clock C (Fig. 2) with the NOR gate 2a, and using this inverted clock to sample the NRZ waveform with the AND gate 3a.
A waveform is obtained. Further, if "1" is given to the output selection signal 15a, the RTO waveform is output.

The EOR waveform is the second clock C (Figure 2) and the NRZ
The waveform is obtained by exclusive ORing the waveforms with the gate 5a. The EOR waveform obtained at this time is shown as waveform F in FIG. Further, it is output by giving "1" to the output control signal 18a and opening the gate 9a.

In multi-clock mode, n
This mode generates RZ waveforms or RTO waveforms (n≧2). The following explanation will be given using the case where n=2 as an example.

The data input 12a and clock input 13a of the D flip-flop 1a are supplied with logic data A and timing clock B (second
3) which is a timing chart of the circuit of FIG. 1 in multi-clock mode. Further, a clock having two positive pulses within one cycle as shown in waveform C in FIG. 3 is supplied as a second clock to the clock input 14a. RZ waveform in multi-clock mode and
The RTO waveform is also generated in the same way as in the normal mode by the NRZ waveform D (FIG. 3), gate 4a, and gates 2a and 3a. The RZ and RTO waveforms in the multi-clock mode generated as described above are shown in waveforms E and F in FIG.

A logic waveform generated from a logic waveform generation circuit having such a function is applied to a logic circuit under test, such as a microprocessor, to test the operation quality of the logic circuit under test. In this case, the timing of the change point of the logic waveform output by the logic waveform generation circuit must be accurate. However, the first
In the circuit shown in the figure, the passage of the clock that controls the timing of the waveform change point is different, especially between the circuit that generates the RZ waveform and the circuit that generates the RTO waveform.
Since the number of elements through which the waveform passes also differs, the timing of the change points does not match accurately, making it impossible to generate a highly accurate applied waveform, making it impossible to perform a good test.

[Purpose of the invention]

It is an object of the present invention to eliminate the above-mentioned drawbacks of the prior art, and to generate not only normal logic waveforms but also multiple logic waveforms within one test period using a multi-clock mode, and to generate one with accurate timing. The object of the present invention is to provide a logic waveform generation circuit that can be obtained.

[Summary of the invention]

A logic waveform generation circuit according to the present invention is configured using a flip-flop and a multiplexer,
A shift register driven by an input clock, a data generation circuit for creating data for the shift register in accordance with a desired output logic waveform, and a clock control circuit for also controlling the input clock. A feedback line is provided from the output of the shift register to the multiplexer constituting the shift register, so that a plurality of logic waveforms are output within a fundamental cycle.

In short, it has a multi-clock mode function in addition to the normal mode, and the clock and logic data that control the timing of the output waveform pass through the same path to obtain a logic waveform with accurate timing. , a shift register is used for generating logic waveforms.

[Embodiments of the invention]

Embodiments of the present invention will be described below based on the drawings.

FIG. 4 is a block diagram of an embodiment of the logic wave generation circuit according to the present invention, FIG. 5 is an explanatory diagram of an example of its supply data, FIG. 6 is a timing chart in the normal mode, and FIG. The figure is a timing chart in the same multi-clock mode.

This circuit consists of three D flip-flops 1b, 3
The data generating circuit 6b includes a 3-bit shift register composed of a clock signal 2b, 5b and two multiplexers 2b and 4b, a data generation circuit 6b, and a clock control circuit 7b.

In this embodiment, the data generation circuit 6b supplies data inputs 8b to 10 of the shift register.
3-bit shift register data corresponding to the output waveform is supplied in parallel to 3 bits of shift register data corresponding to the output waveform.
An operation control signal for controlling three operations (preset, shift, rotate) is supplied, and a shift register clock for controlling the output timing of the output waveform is supplied from the clock input 13b.

Furthermore, the 3-bit shift register data created by the data generation circuit 6b is created by decoding the aforementioned logic data and other data, and may be as shown in FIG. 5, for example. . In addition, in FIG. 5, the x mark represents Don't Care.

Below, we will discuss in detail the case where the RZ waveform is output in normal mode and multi-clock mode.

Timing chart in normal mode is 6th
As shown in the figure. A is logical data, and the data generating circuit 6b decodes this data and other control data to create 3-bit shift register data B. In FIG. 6, three bits of data are combined into one for convenience. Here, it is assumed that the logical value of each bit of the shift register data B, the output waveform, and the logical data have a relationship as shown in FIG. 5 mentioned above. That is, when outputting the RZ waveform, data inputs 8b to 10b are
Shift register data (1, 0, X) is given. Next, an operation selection signal C (FIG. 6) corresponding to the operation of the shift register is applied to the selection terminals 11b and 12b.
is input from the clock control circuit 7b. In the case of the RZ waveform, the order is preset (symbol P) → shift (symbol S), and the preset operation selection signal C
After that, shift register clock E is applied to clock input 13b. In synchronization with this clock E, shift register data "1" is output from the shift register output 15b. After that, the operation selection signal C selects the shift operation, and the shift register clock F causes the data input terminal 9
The shift register "0" input from the output terminal 15b is output from the output terminal 15b, as shown in the waveform G in FIG.
An RZ waveform is obtained. In addition, clock input terminal 1
The clocks E and F mentioned above are used as the clocks input to 3b, but in the case of an RZ waveform, for example, the logical sum of clock E and clock F can be taken, and the same clock is used in the case of an RTO waveform. Also, NRZ
For the waveform, clock E may be used, and for the EOR waveform, a logical sum of clocks D, E, and F may be used as the shift register clock. Waveform H in Figure 6
and I represent changes in the operation selection signal when outputting the EOR waveform and NRZ waveform, respectively. For the RTO waveform, the same operation selection signal as for the RZ waveform may be used. Also, waveforms J, K, L
show the EOR waveform, NRZ waveform, and RTO waveform, respectively.

Next, the case of outputting the RZ waveform in multi-clock mode will be explained. In Figure 7,
A is logic data, and B is shift register data that is decoded from the logic data and input to terminals 8b to 10b, all written together for convenience. The logical values given to each terminal are shown in FIG.

The timing relationship between shift register clocks C to E and operation selection signal F is given as shown in FIG. 7, and is different from that in the normal mode described above. When the operation selection signal selects rotate (symbol R), the logical value outputted to the output terminal 15b at this time is inputted to the D flip-flop 3b via the multiplexer 2b via the signal line 14b. Further, as the shift register clock, a clock obtained by calculating the logical sum of D and E is used. Therefore,
When outputting an RZ waveform, if the logic data is “1” as shift register data, (1, 0,
When X) is used (FIG. 5), the change in the logical value at the output terminal 15b becomes 1→0→1→0, and the RZ waveform shown in waveform G in FIG. 7 is obtained. moreover,
For the RTO waveform, the operation selection signal and shift register clock are the same as for the RZ waveform.
An RTO waveform shown as waveform H in FIG. 7 is obtained.

As explained above, in this embodiment, data is input to the shift register in parallel, and the operation of the shift register is selectively controlled by the operation selection signal.
The output waveform can be changed by selecting the necessary clock according to the output waveform from among multiple clocks that control the timing of the change point of the output waveform, taking the logical sum, and supplying this as the shift register clock. I am getting . Therefore, the multiple change points of each generated waveform pass through the same path regardless of the type of output waveform, so both in normal mode and multi-clock mode,
It is possible to obtain logic waveforms with accurate timing.

〔Effect of the invention〕

As explained above in detail, according to the present invention, the clock that controls the timing of the change point of the output waveform and the route through which the data passes can be made the same, so both in the normal mode and the multi-clock mode. It is also possible to obtain logic waveforms with accurate timing, which has a significant effect on improving the accuracy of logic circuit tests.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an example of a conventional logic waveform generation circuit, FIG. 2 is a timing chart in its normal mode, FIG. 3 is a timing chart in its multi-clock mode, and FIG. Block diagram of one embodiment of the logic waveform generation circuit according to the present invention, No. 5
The figure is an explanatory diagram of an example of the supply data, and Figure 6 is a timing chart in the same normal mode.
FIG. 7 is a timing chart in the multi-clock mode. 1b, 3b, 5b...D flip-flop, 2
b, 4b...multiplexer, 6b...data generation circuit, 7b...clock control circuit.

Claims (1)

[Claims] 1. A shift register configured using a flip-flop and a multiplexer and driven by an input clock, a data generation circuit for generating data for the shift register in accordance with a desired output logic waveform, and a shift register driven by an input clock. A feedback line is provided from the output of the shift register to the multiplexer constituting the shift register, so that a plurality of logic waveforms are output within a fundamental period. Logic waveform generation circuit.