JPH0369930U

JPH0369930U -

Info

Publication number: JPH0369930U
Application number: JP12787589U
Authority: JP
Priority date: 1989-11-02
Filing date: 1989-11-02
Publication date: 1991-07-12

Description

[Brief explanation of drawings]

第１図は本考案の実施例を示す回路図、第２図
は第１図のタイムチヤート、第３図は従来例を示
す回路図、第４図は第３図のタイムチヤートであ
る。図中、ＱＰ_１〜ＱＰ_６……Ｐ型ＦＥＴ、ＱＮ_１〜ＱＮ_６……Ｎ型ＦＥＴ，ＳＲ_１，ＳＲ_２……シ
フトレジスタの各段の単位回路を示す。 FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a time chart of FIG. 1, FIG. 3 is a circuit diagram of a conventional example, and FIG. 4 is a time chart of FIG. 3. In the figure, QP ₁ to QP ₆ ... P-type FET, QN ₁ ~QN ₆ ... N-type FET, SR ₁ , SR ₂ ... Indicates a unit circuit of each stage of the shift register.

Claims

[Scope of utility model registration request]

A shift register formed by continuously connecting a unit circuit comprising a first inverter that reads an input signal at a first level of a clock signal, and a latch circuit that latches the output of the first inverter at a second level of a clock signal. In the first circuit of each unit circuit,
1. A C-MOS shift register characterized in that the stray capacitance generated at the floating connection point of the C-MOS transistors forming the inverter is configured to be charged or discharged in accordance with the level of an input signal.