JPH0369977U

JPH0369977U -

Info

Publication number: JPH0369977U
Application number: JP1989125863U
Authority: JP
Priority date: 1989-10-27
Filing date: 1989-10-27
Publication date: 1991-07-12

Description

[Brief explanation of drawings]

第１図は本考案の一実施例を示す回路図、第２
図は一実施例の動作のタイミングチヤート、第３
図は従来例を示す回路図、第４図は従来例の動作
のタイミングチヤートである。１……ＣＣＤ撮像素子、２……ＣＤＳ回路、３
……信号処理回路、４ａ，４ｂ……タイミング信
号発生回路、Ａ……増幅器、Ｃ……コンデンサ、
ＣＨ……ホールド・コンデンサ、Ｉ_１〜Ｉ_４……
定電流源、ＩＮ_１……ＩＮ_３……インバータ、Ｍ
_ｎ１〜Ｍ_ｎ４……ｎＭＯＳトランジスタ、Ｍ_ｐ１〜Ｍ_ｐ４……ｐＭＯＳトランジスタ、Ｑ_ｎ１〜Ｑ
_ｎ４……ＮＰＮトランジスタ、Ｑ_ｐ１……ＰＮＰ
トランジスタ、φ_１……ブランキング信号、φ_２……クランプ信号。 Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a timing chart of the operation of one embodiment.
The figure is a circuit diagram showing a conventional example, and FIG. 4 is a timing chart of the operation of the conventional example. 1...CCD image sensor, 2...CDS circuit, 3
...Signal processing circuit, 4a, 4b...Timing signal generation circuit, A...Amplifier, C...Capacitor,
CH...Hold capacitor, _I1 to _I4 ...
Constant current source, IN ₁ ... IN ₃ ... Inverter, M
_n1 to M _n4 ... nMOS transistor, M _p1 ~M _p4 ... pMOS transistor, Q _n1 ~Q
_n4 ...NPN transistor, Q _p1 ...PNP
Transistor, φ ₁ ...Blanking signal, φ ₂ ...Clamp signal.

Claims

[Scope of utility model registration request]

In a CCD camera device including a correlated double sampling circuit and a signal processing circuit in which an internal bias is fixed by a clamp signal synchronized with an imaging signal from the correlated double sampling circuit, a first input terminal is connected to the correlated double sampling circuit. a two-input, one-output analog switch circuit connected to the output terminal of the sampling circuit, a second input terminal connected to a variable DC voltage power supply, and an output terminal connected to the signal processing circuit via an air space; and blanking. A CCD camera device comprising means for controlling the switching operation of the analog switch circuit in synchronization with a signal.