JPH037131B2 - - Google Patents
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- Publication number
- JPH037131B2 JPH037131B2 JP57180751A JP18075182A JPH037131B2 JP H037131 B2 JPH037131 B2 JP H037131B2 JP 57180751 A JP57180751 A JP 57180751A JP 18075182 A JP18075182 A JP 18075182A JP H037131 B2 JPH037131 B2 JP H037131B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode
- multilayer ceramic
- ceramic capacitor
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は積層セラミツクコンデンサの端子電極
形成方法に関するもので、特に端子電極をメツキ
にて形成した温度補償用積層セラミツクコンデン
サに発生するＱ不良の改善に供するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for forming terminal electrodes of multilayer ceramic capacitors, and in particular to improvement of Q defects that occur in temperature-compensating multilayer ceramic capacitors in which terminal electrodes are formed by plating. This is what we provide.
従来例の構成とその問題点
従来、積層セラミツクコンデンサの端子電極に
は、第１図に示すようにAg−Pd電極１を用いた
もの、また第２図に示すように半田耐熱性を考慮
してAg電極２形成後、電解または無電解メツキ
にてNi層３、さらにその上に電解メツキによる
Sn−Pb層４を形成したものが一般的であつた。
第１図、第２図で５は積層セラミツクコンデンサ
素子、６は内部電極層である。Conventional configurations and their problems Conventionally, the terminal electrodes of multilayer ceramic capacitors used Ag-Pd electrodes 1 as shown in Figure 1, and those that took soldering heat resistance into consideration as shown in Figure 2. After forming the Ag electrode 2, the Ni layer 3 is formed by electrolytic or electroless plating, and then the Ni layer 3 is formed by electrolytic plating.
Generally, a Sn--Pb layer 4 was formed.
In FIGS. 1 and 2, 5 is a multilayer ceramic capacitor element, and 6 is an internal electrode layer.
ところが、Ag−Pd電極ではPdが20〜30％含有
されるためコスト高であり、さらにはユーザでの
苛酷な半田付け条件を考慮した場合、半田耐熱性
の面で問題があつた。一方、従来のAg電極層上
への電解メツキによる方法では半田耐熱性には優
れ、低コスト化は図れるもののＱ不良が発生して
いた。 However, since the Ag-Pd electrode contains 20 to 30% Pd, it is expensive, and furthermore, when considering the user's harsh soldering conditions, there is a problem in terms of soldering heat resistance. On the other hand, the conventional method of electrolytic plating on the Ag electrode layer has excellent solder heat resistance and can reduce costs, but Q defects have occurred.
発明の目的
本発明は上記欠点に鑑み、メツキ処理を前提と
して、Ｑ不良を改善する積層セラミツクコンデン
サの端子電極形成方法を提供しようとするもので
ある。OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks, the present invention seeks to provide a method for forming terminal electrodes of a multilayer ceramic capacitor that improves the quality factor (Q) defect based on the premise of plating.
発明の構成
この目的を達成するために本発明の積層セラミ
ツクコンデンサの端子電極形成方法は、積層セラ
ミツクコンデンサ素子の端部にAg電極を塗布す
る前に、ガラスペーストを塗布し、焼付けして端
子電極部にガラス質の層を設けたものである。こ
の上に従来と同じ方法にてAg電極塗布、焼付け、
電解または無電解メツキによるNi層形成、電解
メツキによるSn−Pb層の形成を行い、端子電極
を形成するものであり、メツキ処理によるＱ不良
を改善できるものである。Structure of the Invention In order to achieve this object, the method for forming terminal electrodes of a multilayer ceramic capacitor according to the present invention is to apply a glass paste to the ends of a multilayer ceramic capacitor element before applying an Ag electrode, and then bake the terminal electrodes. A vitreous layer is provided on the top. On top of this, apply Ag electrode using the same method as before, bake it,
A terminal electrode is formed by forming a Ni layer by electrolytic or electroless plating and a Sn--Pb layer by electrolytic plating, and can improve Q defects caused by plating.
実施例の説明
以下、本発明の実施例を第３図、第４図を用い
て説明する。図において、７はPdまたはその他
の金属材料にて内部電極８を構成した酸化チタン
系誘電体材料からなる積層セラミツクコンデンサ
素子であり９はこの素子７の端部に塗布され、
600〜800℃で10〜20分間の焼付けによつて形成さ
れたガラス層である。１０はガラス層９上に塗布
後、700〜900℃で10〜20分間焼付けたAg電極層
である。ここで用いられるガラスはAg焼付け温
度以下で軟化する組成のものを使用することは言
うまでもない。このAg焼付け時にAg電極層１０
の下層のガラス層９は軟化し、素子７の内部電極
８とガラス層９及びAg電極層１０が反応し、内
部電極８とAgの合金が生成され、内部電極８と
端子電極とは導通状態となる。１１は電解または
無電解メツキにて生成されたNi層、５は電解メ
ツキによつて生成されたSn−Pb層である。DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to FIGS. 3 and 4. In the figure, 7 is a multilayer ceramic capacitor element made of a titanium oxide dielectric material with internal electrodes 8 made of Pd or other metal materials, and 9 is coated on the end of this element 7.
This is a glass layer formed by baking at 600-800°C for 10-20 minutes. 10 is an Ag electrode layer that was coated on the glass layer 9 and then baked at 700 to 900°C for 10 to 20 minutes. It goes without saying that the glass used here should have a composition that softens below the Ag baking temperature. When baking this Ag, the Ag electrode layer 10
The lower glass layer 9 of the element 7 is softened, the internal electrode 8 of the element 7 reacts with the glass layer 9, and the Ag electrode layer 10, an alloy of the internal electrode 8 and Ag is generated, and the internal electrode 8 and the terminal electrode are in a conductive state. becomes. 11 is a Ni layer produced by electrolytic or electroless plating, and 5 is a Sn--Pb layer produced by electrolytic plating.
この本発明方法で得られたものと、従来のメツ
キ方法で得られたものとのＱの測定結果は、従来
のもので３〜５／1000、本発明のもので０／1000
のＱ不良発生数であつた。また、半田付け性、半
田耐熱性も従来のメツキ品と同様良好であつた。
以上のように、積層セラミツクコンデンサの端子
電極部にガラスペーストを塗布、焼付けしたの
ち、そのガラス層上にAg電極を塗布、焼付けし、
そのAg電極層上にNi及びSn−Pbメツキ処理した
ものはＱ不良発生もなく、半田付け性、半田耐熱
性も極めて良好なものが得られる。 The measurement results of Q between those obtained by the method of the present invention and those obtained by the conventional plating method are 3 to 5/1000 for the conventional method and 0/1000 for the method of the present invention.
The number of Q defective occurrences was . Furthermore, the solderability and soldering heat resistance were as good as conventional plated products.
As described above, after applying glass paste to the terminal electrode part of a multilayer ceramic capacitor and baking it, an Ag electrode is applied and baked on the glass layer.
When the Ag electrode layer is plated with Ni and Sn--Pb, no Q defects occur and extremely good solderability and soldering heat resistance are obtained.
発明の効果
従つて、本発明による方法を用いればメツキ処
理に起因するＱ不良を防止でき、半田付け性、半
田耐熱性の優れたメツキ処理品の製造が可能とな
り、産業上極めて有効な方法である。Effects of the Invention Therefore, by using the method of the present invention, it is possible to prevent Q defects caused by plating, and it is possible to manufacture plated products with excellent solderability and soldering heat resistance, which is an extremely effective method in industry. be.
第１図は従来の端子電極にAg−Pdを用いた積
層セラミツクコンデンサの断面図、第２図は従来
の端子電極にメツキ処理を行つた積層セラミツク
コンデンサ断面図、第３図は本発明方法による端
子電極部にガラス層を形成した積層セラミツクコ
ンデンサの断面図、第４図は本発明方法による端
子電極を形成した積層セラミツクコンデンサの断
面図である。
７……積層セラミツクコンデンサ素子、９……
ガラス層、１０……Ag電極、１１……Ni層、１
２……Sn−Pb層。
Figure 1 is a cross-sectional view of a conventional multilayer ceramic capacitor using Ag-Pd for terminal electrodes, Figure 2 is a cross-sectional view of a conventional multilayer ceramic capacitor in which the terminal electrodes are plated, and Figure 3 is a cross-sectional view of a multilayer ceramic capacitor using the method of the present invention. FIG. 4 is a sectional view of a multilayer ceramic capacitor in which a glass layer is formed on the terminal electrode portion. FIG. 4 is a sectional view of a multilayer ceramic capacitor in which a terminal electrode is formed by the method of the present invention. 7... Multilayer ceramic capacitor element, 9...
Glass layer, 10...Ag electrode, 11...Ni layer, 1
2...Sn-Pb layer.
Claims (1)
ラスペーストを塗布、焼付けしたのち、そのガラ
ス層上にAg電極ペーストを塗布、焼付けし、そ
のAg電極層上に電解または無電解メツキにてNi
層を形成し、さらにその上に電解メツキにてSn
−Pb層を形成することを特徴とする積層セラミ
ツクコンデンサの端子電極形成方法。1. After applying glass paste to the terminals of a multilayer ceramic capacitor element and baking it, apply and bake Ag electrode paste on the glass layer, and then apply Ni on the Ag electrode layer by electrolytic or electroless plating.
Form a layer, and then apply Sn on top by electrolytic plating.
- A method for forming terminal electrodes of a multilayer ceramic capacitor, characterized by forming a Pb layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57180751A JPS5969906A (en) | 1982-10-14 | 1982-10-14 | Method of forming terminal electrode of laminated ceramic condenser |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57180751A JPS5969906A (en) | 1982-10-14 | 1982-10-14 | Method of forming terminal electrode of laminated ceramic condenser |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5969906A JPS5969906A (en) | 1984-04-20 |
| JPH037131B2 true JPH037131B2 (en) | 1991-01-31 |
Family
ID=16088675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57180751A Granted JPS5969906A (en) | 1982-10-14 | 1982-10-14 | Method of forming terminal electrode of laminated ceramic condenser |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5969906A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0385715A (en) * | 1989-08-30 | 1991-04-10 | Matsushita Electric Ind Co Ltd | Electrode formation method for electronic components |
| JP4661815B2 (en) * | 2007-03-29 | 2011-03-30 | Ｔｄｋ株式会社 | Manufacturing method of electronic parts |
| KR101228752B1 (en) * | 2011-11-04 | 2013-01-31 | 삼성전기주식회사 | Multilayered ceramic electronic component and fabricating method thereof |
-
1982
- 1982-10-14 JP JP57180751A patent/JPS5969906A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5969906A (en) | 1984-04-20 |
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