JPH0376018B2 - - Google Patents

Info

Publication number
JPH0376018B2
JPH0376018B2 JP56105703A JP10570381A JPH0376018B2 JP H0376018 B2 JPH0376018 B2 JP H0376018B2 JP 56105703 A JP56105703 A JP 56105703A JP 10570381 A JP10570381 A JP 10570381A JP H0376018 B2 JPH0376018 B2 JP H0376018B2
Authority
JP
Japan
Prior art keywords
thin film
silicon thin
type
film
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56105703A
Other languages
Japanese (ja)
Other versions
JPS589320A (en
Inventor
Kazunobu Tanaka
Akihisa Matsuda
Toshihiko Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tonen General Sekiyu KK
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Tonen Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology, Tonen Corp filed Critical Agency of Industrial Science and Technology
Priority to JP56105703A priority Critical patent/JPS589320A/en
Priority to US06/394,074 priority patent/US4490208A/en
Priority to DE8282303526T priority patent/DE3276280D1/en
Priority to EP82303526A priority patent/EP0069580B1/en
Publication of JPS589320A publication Critical patent/JPS589320A/en
Priority to US06/790,781 priority patent/US4598304A/en
Publication of JPH0376018B2 publication Critical patent/JPH0376018B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H10P14/3441—Conductivity type
    • H10P14/3442—N-type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H10P14/3441—Conductivity type
    • H10P14/3444—P-type

Landscapes

  • Photovoltaic Devices (AREA)
  • Light Receiving Elements (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明はダイオード、太陽電池、画像形成用光
導電体又は読取装置用光電変換素子等に適用する
ことのできるシリコン薄膜の製造方法に関するも
のである。 従来、シリコン薄膜が所期の目的を達成するた
めに単独で、又は一般にpin接合素子又はpn接合
素子として使用されている。このようなpin又は
pn接合素子は通常グロー放電法によりプラズマ
雰囲気下にて例えば不純物としてＢ（ホウ素）を
添加したｐ型シリコン薄膜を形成し、次で該ｐ型
シリコン薄膜上に活性層である添加しないｉ型シ
リコン薄膜及びＰ（リン）を添加したｎ型シリコ
ン薄膜を、又は前記ｐ型シリコン薄膜上に直接前
記ｎ型シリコン薄膜を成長させる二つ又は三つの
成膜工程によつて作製されている。別法として最
初にｎ層膜を、次でｉ型層及びｐ層膜を又は前記
ｎ層膜上に直接ｐ層膜を成膜する作製方法も又同
じように行なわれた。しかしながら、このような
成膜方法によつて作製された素子は、既成長の下
層膜上に新しい上層を成膜する際に下層（既成
長）膜の不純物がプラズマ雰囲気下で放出され、
上層の膜に混入するという欠点をもつている。そ
の結果、不純物を含まない基板上に成長させた膜
に比べ不純物を含む膜上に成長させた膜は、光電
気伝導度及び暗電気伝導度の低下が生じる。この
ために特に、太陽電池を目的とするpin接合半導
体素子を製造した場合、基板、ｐ層膜、ｉ層膜、
ｎ層膜の順に作製された素子についていえば、ｉ
層膜中にｐ層膜に添加した不純物が混入するため
に光電気伝導度及び暗電気伝導度が低下するとと
もに、良好な接合面が形成されない。他方、基
板、ｎ層膜、ｉ層膜、ｐ層膜の順に作製された素
子についていえば、ｉ層膜中にｎ層膜に添加した
不純物が混入し、フエルミレベルの位置を移動さ
せるため、充分な開放電圧を得ることができな
い。これらのことは結局、光のエネルギー変換効
率が低下することを意味し、太陽電池としての性
能を低下せしめると同様、他の諸用途に使用した
場合にも性能の低下をもたらすものであつた。 本発明者等は、不純物元素を添加したｐ型シリ
コン薄膜又はｎ型シリコン薄膜を弗素、塩素、臭
素、沃素及び水素の少なくとも一種の元素のガス
のプラズマ放電状態下におくと、ｐ型又はｎ型シ
リコン薄膜はその表面から5000Åまでの深さの不
純物量が減少し、そして該ｐ型又はｎ型シリコン
薄膜の不純物が除去されたことによりできたダン
グリングボンドはプラズマ放電ガスにより置換さ
れ、それによつてプラズマ雰囲気下におけるシリ
コン薄膜からのこれ以上の不純物を放出させない
ための障壁層を形成するということを見出した。 更に又、シリコン薄膜からの不純物の減少程度
及び減少深さは、真空容器のプラズマ放電時圧力
及び時間、並びにプラズマ放電電力密度を調整す
ることによつて種々に変え得ることが分つた。 本発明に係る製造方法を実施する際の上記重要
なパラメータの一つである放電時圧力は1.5×
10-2Torr〜3Torrに制御されるのが好ましい。つ
まり、放電時圧力が1.5×10-2Torr以下であると
真空容器内の流れが拡散流となりシリコン薄膜基
板より放出された不純物が再びシリコン薄膜基板
へと混入する可能性が大となるために、真空容器
内の流れを粘性流とするべく放電時圧力は1.5×
10-2Torr以上であることが必要となる。又上限
としての放電時圧力3Torrは、電極とアースシー
ルドとの放電を防止するためであり、主に、装置
因子によるものである。又放電電力密度は使用さ
れるプラズマガスの性質により変化するが、0.5
〜50W／cm2が適当である。このような条件下にお
ける放電時間は１秒〜５時間の間で種々に変える
ことができる。又、放電電力密度と放電時間との
関係について言えば、一般に放電電力密度は原始
添加不純物元素の減少深さに関与し、放電時間は
原始添加不純物元素の減少量に関与するというこ
とができる。 又、プラズマ状態にもたらされるプラズマ元素
ガスの真空容器内への流量はプラズマ状態を安定
に保つように設定されることが必要であり、0.5
〜100SCCMにて好結果が得られた。 本発明は以上の如き新しい諸知見に基いてなさ
れたものである。即ち、本発明に係るシリコン薄
膜の製造方法は、弗素、塩素、臭素、沃素および
水素の少なくとも一種の元素のガスのプラズマ放
電状態中にｐ型シリコン薄膜又はｎ型シリコン薄
膜をおき、ｐ型又はｎ型シリコン薄膜の表面から
5000Åまでの任意の深さまでの不純物量を減少さ
せかつ不純物が除かれたことによりできたダング
リングボンドをプラズマ放電ガスにより置換する
ことを顕著な特徴とする。 従つて、本発明に従つて製造されたｐ型又はｎ
型シリコン薄膜は、次工程において該薄膜の上に
例えばｉ層膜を成膜する場合のように低電力プラ
ズマ放電に晒されても薄膜内の不純物をｉ層膜中
へと再放出することはない。 即ち、従来の方法にて作製されたｎ型又はｐ型
薄膜基板上に他の膜をプラズマ雰囲気下で成長さ
せると、この膜中に基板となつた膜の不純物を
1016原子／cm3以上含むのに比べ本発明の製造方法
で作製されたｎ型又はｐ型薄膜を基板とした上
に、他の膜を成長させた場合には、この膜中への
基板となつた膜の不純物の放出量を1016原子／cm3
以下に抑制することが可能である。 従つて、本発明の主たる目的は、任意のプラズ
マ雰囲気下に晒されても、添加された不純物を外
部へと放出しない（又は放出しても極めてわずか
とされる）ｐ型又はｎ型シリコン薄膜の製造方法
を提供することである。 本発明の他の目的は、良好な光電気伝導度及び
暗電気伝導度を有し且つ光エネルギ変換効率の向
上した太陽電池、画像形成用光導電体、読取装置
用光電変換素子又はダイオード等の作製に使用す
ることのできるシリコン薄膜の製造方法を提供す
ることである。 本発明に係る製造方法においてはシリコンの単
結晶半導体、及びシラン（SiH4）にドーパント
ガスを混合したものを原料ガスとしプラズマ雰囲
気下にて任意の基板上に成膜された非晶質のシリ
コン半導体等のｐ型又はｎ型シリコン薄膜を使用
することができるが、更に本出願人に係る特許出
願（特願昭55−143010号）に記載されるようなシ
リコン薄膜、即ち、シランSiH4またはハロゲン
化シランSiH0〜3X4〜1（Ｘ：ハロゲン元素）のいず
れか、またはその２種以上の混合ガスを原料ガス
とし、これにドーパントガスを混合し、成膜速度
を十分に制御し結晶、非晶質混合層を生成する目
的で、前記混合ガスを、ヘリウム、ネオン、アル
ゴン等の希ガスまたは水素等で約１対１より大き
い割合で希釈するとともに、約0.2W／cm2以上の
プラズマ放電電力密度の電力を投入しながら成膜
されたシリコン薄膜をも都合よく適用し得るもの
である。 次に、本発明に係るシリコン薄膜の製造方法を
実施例に則して説明する。 実施例 １ 第１図において、混合容器１を含めた全装置系
を油回転ポンプ２および油拡散ポンプ３を使つて
約10-6Torrの真空度にし、次でシランボンベ４
および水素ボンベ５、さらにドーパントガス（シ
ボラン又はホスフイン）ボンベ６または７よりガ
ス混合容器１に所要の割合で導入し、混合する。
混合されたガスは流量計８を通して真空容器９中
に一定流量で導入される。メインバルブ１０で操
作して真空容器９中の真空度を真空計１１で監視
しながら所要の圧力に維持する。高周波発振器１
２で電極１３および１３′間に高周波電圧を印加
してグロー放電を発生させる。基板１５はヒータ
ー１４で加熱された基板上に載置され、ヒーター
で所要の温度に加熱されており、この基板１５上
にドープされたシリコン薄膜が成膜される。 本実施例において、原料ガスはSiH4：H2＝
１：１の混合ガスを用いドーパントとしてシボラ
ン（B2H6）をSiH4に対して２％（体積基準）混
合したものであつた。又水素プラズマ雰囲気下に
て処理する前のｐ型シリコン薄膜の成膜条件はプ
ラズマ放電電力密度0.1W／cm2、原料ガス流量
15SCCM、基板温度300℃、成膜圧力５×
10-2Torrであつた。 上記の如くにてレシリコン薄膜を成膜した後再
び混合容器１を含めた全装置系をポンプ２および
３を使つて約10-6Torrの真空度まで真空にし、
水素ボンベ５より水素ガスを管路１６を介して直
接流量計８に供給し、次で真空容器９中に一定流
量導入する。メインバルブ１０を操作して真空容
器９中の真空度を真空計１１を監視しながら
1Torrに調整する。次で、高周波発振器１２で電
極１３及び１３′間に高周波電圧13.56メガヘルツ
を印加して水素プラズマグロー放電を発生させ
る。これにより表面から不純物が除去され、その
結果生じたダングリングボンドが水素により置換
されたｐ型の非晶質シリコン薄膜が作製された。
水素プラズマ放電条件つまり放電時間を変えて４
種のｐ型非晶質シリコン薄膜を作製した。結果は
第１表に示される。この表で、No.１が水素プラズ
マ放電処理をしない従来の方法により製造したｐ
型シリコン薄膜である。No.２〜No.５が本発明によ
り製造したｐ型シリコン薄膜の実施例であり、水
素ガス流量および水素プラズマ放電時圧力を調整
することにより、装置内の流れを粘性流領域に
し、真空容器の壁及びシリコン薄膜より放出され
たボロンをシリコン薄膜中に再混入しないような
操作がなされた。 第２図は、本発明に従つて作製されたシリコン
薄膜の電気伝導度を水素プラズマ処理時間の関数
として示すものである。第２図から、本発明の製
造法により、表面からシリコン薄膜中のボロン原
子量が減少していることが考察される。また、
SIMS測定により、本発明によるｐ型薄膜は、表
面から1000Åの深さまでのボロン原子が完全に除
去されていることが確認された（第３図を参照せ
よ）。 The present invention relates to a method for producing a silicon thin film that can be applied to diodes, solar cells, photoconductors for image formation, photoelectric conversion elements for reading devices, and the like. Traditionally, silicon thin films have been used alone or generally as pin or pn junction devices to achieve the intended purpose. A pin like this or
A p-n junction element is usually formed by forming a p-type silicon thin film doped with B (boron) as an impurity in a plasma atmosphere using a glow discharge method, and then forming an active layer of undoped i-type silicon on the p-type silicon thin film. It is produced by two or three film forming steps of growing a thin film and an n-type silicon thin film doped with P (phosphorus), or directly growing the n-type silicon thin film on the p-type silicon thin film. Alternatively, a method of forming an n-layer film first, then an i-type layer and a p-layer film, or a p-layer film directly on the n-layer film was also carried out in the same manner. However, in devices manufactured by such a film formation method, when a new upper layer is formed on an already grown lower film, impurities in the lower (already grown) film are released in a plasma atmosphere.
It has the disadvantage of being mixed into the upper film. As a result, a film grown on a film containing impurities has lower photoelectric conductivity and dark electrical conductivity than a film grown on a substrate that does not contain impurities. For this reason, in particular, when manufacturing a pin junction semiconductor device intended for solar cells, the substrate, p-layer film, i-layer film,
Regarding the device manufactured in the order of n-layer films, i
Since the impurity added to the p-layer film is mixed into the layer film, the photoelectric conductivity and dark electrical conductivity are reduced, and a good bonding surface is not formed. On the other hand, for devices fabricated in the order of substrate, n-layer film, i-layer film, and p-layer film, the impurities added to the n-layer film will mix into the i-layer film and move the position of the Fermi level. It is not possible to obtain a suitable open circuit voltage. These things ultimately mean that the light energy conversion efficiency decreases, which not only causes a decrease in performance as a solar cell, but also results in a decrease in performance when used for various other purposes. The present inventors have discovered that when a p-type silicon thin film or an n-type silicon thin film doped with an impurity element is placed under a plasma discharge state of a gas of at least one element among fluorine, chlorine, bromine, iodine, and hydrogen, p-type or n-type The amount of impurities in the p-type or n-type silicon thin film is reduced to a depth of 5000 Å from the surface, and the dangling bonds created by removing the impurities from the p-type or n-type silicon thin film are replaced by plasma discharge gas, and Therefore, it has been discovered that a barrier layer can be formed to prevent further release of impurities from a silicon thin film in a plasma atmosphere. Furthermore, it has been found that the degree and depth of reduction of impurities from the silicon thin film can be varied by adjusting the pressure and time during plasma discharge in the vacuum chamber and the plasma discharge power density. The discharge pressure, which is one of the important parameters mentioned above when implementing the manufacturing method according to the present invention, is 1.5×
It is preferably controlled to between 10 −2 Torr and 3 Torr. In other words, if the discharge pressure is 1.5×10 -2 Torr or less, the flow inside the vacuum container becomes a diffusion flow, and there is a high possibility that impurities released from the silicon thin film substrate will mix into the silicon thin film substrate again. , the pressure during discharge is 1.5× to make the flow inside the vacuum container a viscous flow.
It needs to be 10 -2 Torr or higher. The upper limit of the discharge pressure of 3 Torr is to prevent discharge between the electrode and the earth shield, and is mainly due to equipment factors. Also, the discharge power density varies depending on the properties of the plasma gas used, but it is 0.5
~50W/ cm2 is appropriate. The discharge time under such conditions can be varied between 1 second and 5 hours. Regarding the relationship between the discharge power density and the discharge time, it can be said that the discharge power density is generally related to the depth of reduction of the originally added impurity element, and the discharge time is related to the amount of reduction of the originally added impurity element. In addition, the flow rate of the plasma element gas brought into the plasma state into the vacuum container must be set to keep the plasma state stable, and is 0.5
Good results were obtained at ~100SCCM. The present invention has been made based on the above-mentioned new findings. That is, in the method for producing a silicon thin film according to the present invention, a p-type silicon thin film or an n-type silicon thin film is placed in a plasma discharge state of a gas containing at least one element among fluorine, chlorine, bromine, iodine, and hydrogen. From the surface of n-type silicon thin film
A distinctive feature is that the amount of impurities is reduced to an arbitrary depth of up to 5000 Å, and the dangling bonds created by the removal of impurities are replaced by plasma discharge gas. Therefore, p-type or n-type produced according to the present invention
Even if a type silicon thin film is exposed to a low-power plasma discharge, such as when an i-layer film is formed on the thin film in the next process, impurities in the thin film will not be re-released into the i-layer film. do not have. In other words, when another film is grown in a plasma atmosphere on an n-type or p-type thin film substrate produced by the conventional method, impurities from the film used as the substrate are absorbed into this film.
When another film is grown on the n-type or p-type thin film produced by the production method of the present invention as a substrate, the substrate in this film contains 10 16 atoms/cm 3 or more. The amount of impurity released from the film is 10 16 atoms/cm 3
It is possible to suppress it to the following. Therefore, the main object of the present invention is to provide a p-type or n-type silicon thin film that does not release added impurities to the outside (or is considered to be extremely small) even when exposed to any plasma atmosphere. An object of the present invention is to provide a method for manufacturing. Another object of the present invention is to provide solar cells, image forming photoconductors, photoelectric conversion elements or diodes for reading devices, etc., which have good photoelectric conductivity and dark electric conductivity and have improved light energy conversion efficiency. An object of the present invention is to provide a method for manufacturing a silicon thin film that can be used for manufacturing. In the manufacturing method according to the present invention, amorphous silicon is formed on an arbitrary substrate in a plasma atmosphere using a silicon single crystal semiconductor and a mixture of silane (SiH 4 ) and a dopant gas as raw material gases. Although a p-type or n-type silicon thin film such as a semiconductor can be used, it is also possible to use a silicon thin film as described in the patent application (Japanese Patent Application No. 143010/1987) filed by the present applicant, i.e., silane SiH 4 or Halogenated silane SiH 0 ~ 3 For the purpose of generating a crystalline/amorphous mixed layer, the mixed gas is diluted with a rare gas such as helium, neon, argon, etc. or hydrogen at a ratio of more than about 1:1, and at a rate of about 0.2 W/cm 2 or more. A silicon thin film formed while applying power with a plasma discharge power density of . Next, a method for manufacturing a silicon thin film according to the present invention will be explained based on examples. Example 1 In FIG. 1, the entire equipment system including the mixing vessel 1 is brought to a vacuum level of approximately 10 -6 Torr using the oil rotary pump 2 and the oil diffusion pump 3, and then the silane cylinder 4 is
and a hydrogen cylinder 5, and further a dopant gas (ciborane or phosphine) cylinder 6 or 7, which are introduced into the gas mixing container 1 at a required ratio and mixed.
The mixed gas is introduced into the vacuum vessel 9 through the flow meter 8 at a constant flow rate. The main valve 10 is operated to maintain the required pressure while monitoring the degree of vacuum in the vacuum container 9 with a vacuum gauge 11. High frequency oscillator 1
At step 2, a high frequency voltage is applied between the electrodes 13 and 13' to generate glow discharge. The substrate 15 is placed on a substrate heated by the heater 14 and heated to a required temperature by the heater, and a doped silicon thin film is formed on the substrate 15. In this example, the source gas is SiH 4 :H 2 =
Siborane (B 2 H 6 ) was mixed as a dopant at 2% (by volume) with respect to SiH 4 using a 1:1 mixed gas. In addition, the deposition conditions for the p-type silicon thin film before treatment in a hydrogen plasma atmosphere are a plasma discharge power density of 0.1 W/cm 2 and a raw material gas flow rate.
15SCCM, substrate temperature 300℃, film formation pressure 5×
It was 10 -2 Torr. After forming the resilicon thin film as described above, the entire equipment system including the mixing container 1 is again evacuated to a vacuum level of approximately 10 -6 Torr using pumps 2 and 3.
Hydrogen gas is directly supplied from the hydrogen cylinder 5 to the flow meter 8 via the pipe line 16, and then introduced into the vacuum container 9 at a constant flow rate. Operate the main valve 10 and monitor the vacuum level in the vacuum container 9 with the vacuum gauge 11.
Adjust to 1Torr. Next, a high frequency voltage of 13.56 MHz is applied between the electrodes 13 and 13' by the high frequency oscillator 12 to generate a hydrogen plasma glow discharge. This removed impurities from the surface and produced a p-type amorphous silicon thin film in which the resulting dangling bonds were replaced by hydrogen.
4 by changing the hydrogen plasma discharge conditions, that is, the discharge time.
A seed p-type amorphous silicon thin film was prepared. The results are shown in Table 1. In this table, No. 1 is the product manufactured by the conventional method without hydrogen plasma discharge treatment.
The type is silicon thin film. No. 2 to No. 5 are examples of p-type silicon thin films manufactured according to the present invention, and by adjusting the hydrogen gas flow rate and the pressure during hydrogen plasma discharge, the flow inside the device is made into a viscous flow region, and the vacuum vessel Operations were performed to prevent boron released from the walls and the silicon thin film from being reintroduced into the silicon thin film. FIG. 2 shows the electrical conductivity of silicon thin films made in accordance with the present invention as a function of hydrogen plasma treatment time. From FIG. 2, it can be considered that the amount of boron atoms in the silicon thin film is reduced from the surface by the manufacturing method of the present invention. Also,
SIMS measurements confirmed that boron atoms from the surface to a depth of 1000 Å were completely removed from the p-type thin film according to the present invention (see FIG. 3).

【表】 実施例 ２ ドーパントとしてホスフイン（PH3）を使用す
る以外は実施例１と同様の方法にてｎ型のシリコ
ン薄膜を成膜し、次で実施例１と同様の方法にて
該ｎ型シリコン薄膜に水素プラズマ処理を施し
た。 SIMS測定により本発明によるｎ型薄膜は表面
から500Åの深さまで燐原子が完全に除去されて
いることが確認された。 以上の如くに本発明の製造方法によつて製造さ
れたｐ型又はｎ型のシリコン薄膜は従来の成膜工
程によつてpn型の又はpin型の接合素子を製造す
ることができることが理解されるであろう。本発
明により成膜されたｐ型（又はｎ型）膜上に順に
ｉ型膜、ｎ型（又はｐ型）膜を成膜して作製され
たpin接合半導体素子は従来のpin接合半導体素子
よりも良好なpi（又はni）接合を有し、同様に本
発明により成膜されたｐ型（又はｎ型）膜上にｎ
型（又はｐ型）膜を成膜したpn接合半導体素子
は従来のpn接合半導体素子よりも、良好なpn接
合を有する。又ｐ型膜基板に本発明を適用し、該
基板膜表面から不純物を充分に除去してpi型シリ
コン薄膜とすることもでき、この場合にはpi膜上
にｎ型膜を成膜することによつてpin接合半導体
素子を作ることもできる。[Table] Example 2 An n-type silicon thin film was formed in the same manner as in Example 1 except that phosphine (PH 3 ) was used as a dopant, and then the n-type silicon thin film was formed in the same manner as in Example 1. The molded silicon thin film was subjected to hydrogen plasma treatment. SIMS measurements confirmed that phosphorus atoms were completely removed from the surface of the n-type thin film according to the present invention to a depth of 500 Å. As described above, it is understood that a p-type or n-type silicon thin film produced by the production method of the present invention can be used to produce a pn-type or pin-type junction element using a conventional film forming process. There will be. A pin junction semiconductor device manufactured by sequentially forming an i-type film and an n-type (or p-type) film on a p-type (or n-type) film formed according to the present invention is better than a conventional pin junction semiconductor device. also has a good pi (or ni) junction, and similarly, n
A pn junction semiconductor device formed with a type (or p-type) film has a better pn junction than a conventional pn junction semiconductor device. Furthermore, the present invention can be applied to a p-type film substrate, and impurities can be sufficiently removed from the substrate film surface to form a pi-type silicon thin film. In this case, an n-type film can be formed on the pi film. It is also possible to make pin junction semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明に係るシリコン薄膜製造方法を
実施する装置を示す概略図である。第２図は本発
明に係る製造方法により作製されたシリコン薄膜
の電気伝導度をプラズマ放電時間の関数として示
すグラフである。第３図は本発明に係る製造方法
により作製されたシリコン薄膜のSIMSの測定結
果を示すグラフである。 １：混合容器、４，５，６，７：ガスボンベ、
９：真空容器、１３，１３′：電極、１５：基板。 FIG. 1 is a schematic diagram showing an apparatus for implementing the silicon thin film manufacturing method according to the present invention. FIG. 2 is a graph showing the electrical conductivity of a silicon thin film produced by the production method according to the present invention as a function of plasma discharge time. FIG. 3 is a graph showing SIMS measurement results of a silicon thin film manufactured by the manufacturing method according to the present invention. 1: Mixing container, 4, 5, 6, 7: Gas cylinder,
9: Vacuum container, 13, 13': Electrode, 15: Substrate.

Claims (1)

【特許請求の範囲】 １ 不純物元素がドープされたｐ型又はｎ型シリ
コン薄膜を弗素、塩素、臭素、沃素及び水素の群
から選択された少なくとも一種の元素のプラズマ
雰囲気下に置き、該プラズマ雰囲気の圧力を1.5
×10-2Torr〜3Torrの範囲に設定して反応帯域に
粘性流領域を形成させ、電力密度を0.5W／cm2〜
50W／cm2の範囲に設定し、それによつて前記シリ
コン薄膜の表面から最大5000Åの深さにわたつて
不純物元素の量を減少させ且つプラズマ元素が不
純物元素と置換するようにしたことを特徴とする
シリコン薄膜の製造方法。 ２ シリコン薄膜は、単結晶のシリコン半導体で
ある特許請求の範囲第１項記載の製造方法。 ３ シリコン薄膜は、非晶質のシリコン半導体で
ある特許請求の範囲第１項記載の製造方法。 ４ シリコン薄膜は非晶質層中に微結晶粒が混在
しているシリコン半導体である特許請求の範囲第
１項記載の製造方法。[Claims] 1. A p-type or n-type silicon thin film doped with an impurity element is placed in a plasma atmosphere of at least one element selected from the group of fluorine, chlorine, bromine, iodine, and hydrogen; pressure of 1.5
×10 -2 Torr to 3 Torr to form a viscous flow region in the reaction zone, and the power density to 0.5 W/cm 2 to
50 W/cm 2 , thereby reducing the amount of the impurity element from the surface of the silicon thin film to a maximum depth of 5000 Å, and causing the plasma element to replace the impurity element. A method for manufacturing a silicon thin film. 2. The manufacturing method according to claim 1, wherein the silicon thin film is a single crystal silicon semiconductor. 3. The manufacturing method according to claim 1, wherein the silicon thin film is an amorphous silicon semiconductor. 4. The manufacturing method according to claim 1, wherein the silicon thin film is a silicon semiconductor in which microcrystalline grains are mixed in an amorphous layer.
JP56105703A 1981-07-08 1981-07-08 Manufacture of silicon thin-film Granted JPS589320A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP56105703A JPS589320A (en) 1981-07-08 1981-07-08 Manufacture of silicon thin-film
US06/394,074 US4490208A (en) 1981-07-08 1982-07-01 Method of producing thin films of silicon
DE8282303526T DE3276280D1 (en) 1981-07-08 1982-07-05 Method of producing thin films of silicon
EP82303526A EP0069580B1 (en) 1981-07-08 1982-07-05 Method of producing thin films of silicon
US06/790,781 US4598304A (en) 1981-07-08 1985-10-23 Thin film devices of silicon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56105703A JPS589320A (en) 1981-07-08 1981-07-08 Manufacture of silicon thin-film

Publications (2)

Publication Number Publication Date
JPS589320A JPS589320A (en) 1983-01-19
JPH0376018B2 true JPH0376018B2 (en) 1991-12-04

Family

ID=14414716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56105703A Granted JPS589320A (en) 1981-07-08 1981-07-08 Manufacture of silicon thin-film

Country Status (1)

Country Link
JP (1) JPS589320A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06104909B2 (en) * 1983-10-11 1994-12-21 株式会社日立製作所 Dry process treatment method and apparatus thereof
JPS6347920A (en) * 1986-08-18 1988-02-29 Hitachi Ltd Method for manufacturing crystalline semiconductor device
JP2892980B2 (en) * 1995-12-18 1999-05-17 株式会社日立製作所 Dry process treatment method
CN110327475B (en) * 2019-07-25 2021-06-04 山东大学齐鲁医院 A kind of device and method for sterilization and bacteriostasis of solid material

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54158190A (en) * 1978-06-05 1979-12-13 Yamazaki Shunpei Semiconductor device and method of fabricating same
JPS55154726A (en) * 1979-05-22 1980-12-02 Shunpei Yamazaki Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS589320A (en) 1983-01-19

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