JPH0376019B2 - - Google Patents

Info

Publication number
JPH0376019B2
JPH0376019B2 JP56105704A JP10570481A JPH0376019B2 JP H0376019 B2 JPH0376019 B2 JP H0376019B2 JP 56105704 A JP56105704 A JP 56105704A JP 10570481 A JP10570481 A JP 10570481A JP H0376019 B2 JPH0376019 B2 JP H0376019B2
Authority
JP
Japan
Prior art keywords
thin film
silicon thin
gas
impurity
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56105704A
Other languages
Japanese (ja)
Other versions
JPS589321A (en
Inventor
Kazunobu Tanaka
Akihisa Matsuda
Toshihiko Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tonen General Sekiyu KK
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Tonen Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology, Tonen Corp filed Critical Agency of Industrial Science and Technology
Priority to JP56105704A priority Critical patent/JPS589321A/en
Priority to US06/394,074 priority patent/US4490208A/en
Priority to DE8282303526T priority patent/DE3276280D1/en
Priority to EP82303526A priority patent/EP0069580B1/en
Publication of JPS589321A publication Critical patent/JPS589321A/en
Priority to US06/790,781 priority patent/US4598304A/en
Publication of JPH0376019B2 publication Critical patent/JPH0376019B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H10P14/3441—Conductivity type
    • H10P14/3442—N-type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H10P14/3441—Conductivity type
    • H10P14/3444—P-type

Landscapes

  • Photovoltaic Devices (AREA)
  • Light Receiving Elements (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明はダイオード、太陽電池、画像形成用光
導電体又は読取装置用光電変換素子等に適用する
ことのできるシリコン薄膜の製造方法に関するも
のである。 従来、シリコン薄膜が所期の目的を達成するた
めにpin接合素子又はPN接合素子として使用され
ている。このようなpin又はpn接合素子は通常グ
ロー放電法によりプラズマ雰囲気下にて例えば不
純物としてＢ（ホウ素）を添加したｐ型シリコン
薄膜を形成し、次いで該ｐ型シリコン薄膜上に活
性層である添加したいｉ型シリコン薄膜及びＰ
（リン）を添加したｎ型シリコン薄膜を、又は前
記ｐ型シリコン薄膜上に直接前記ｎ型シリコン薄
膜を成長させる二つ又は三つの成膜工程によつて
作製されている。別法として最初にｎ層膜を、次
でｉ型層及びｐ層膜を又は前記ｎ層膜上に直接ｐ
層膜を成膜する作製方法も又同じように行なわれ
た。しかしながら、このような成膜方法によつて
作製された素子は、既成長の下層膜上に新しい上
層を成膜する際に下層（既成長）膜の不純物がプ
ラズマ雰囲気下で放出され、上層の膜に混入する
という欠点をもつている。その結果、不純物を含
まない基板上に成長させた膜に比べ不純物を含む
膜上に成長させた膜は、光電気伝導度及び暗電気
伝導度の低下が生じる。このため特に、太陽電池
を目的とするpin接合半導体素子を製造した場合、
基板、ｐ層膜、ｉ層膜、ｎ層膜の順に作製された
素子についていえば、ｉ層膜中にｐ層膜に添加し
た不純物が混入するために、光電気伝導度及び暗
電気伝導度が低下するとともに、良好な接合面が
形成されない。他方、基板、ｎ層膜、ｉ層膜、ｐ
層膜の順に作製された素子についていえば、ｉ層
膜中にｎ層膜に添加した不純物が混入し、フエル
ミレベルの位置を移動させるため、十分な開放電
圧を得ることができない。これらのことは結局、
光のエネルギー変換効率が低下することを意味
し、太陽電池としての性能を低下せしめると同様
他の諸用途に使用した場合にも性能の低下をもた
らすものであつた。 本発明者等は、不純物元素を添加したｐ型シリ
コン薄膜基板又はｎ型シリコン薄膜基板を弗素、
塩素及び水素の群から選択された少なくとも一元
素のガスと、前記シリコン薄膜基板中の不純物と
は別種の不純物から成るガスとの混合ガスのプラ
ズマ放電状態下におくと、該シリコン薄膜基板は
その表面から5000Åまでの深さの不純物量が減少
し、と同時に混合ガス中の別種の不純物がシリコ
ン薄膜基板の表面から任意の深さにわたつてドー
ピングされることを見出した。 更に又、シリコン薄膜基板からの不純物の減少
程度及び減少深さ、並びに該シリコン薄膜基板へ
の新たな別種の不純物のドーピング量及び新たな
不純物のドーピング深さは、１プラズマ放電状態
におかれる混合ガスの組成、２真空容器のプラズ
マ放電時圧力、及び時間、並びに３プラズマ放電
電力密度を調整することによつて種々に変え得る
ことが分つた。 本発明は以上の如き新しい知見に基いてなされ
たものである。即ち、本発明に係るシリコン薄膜
の製造方法は、不純物Ａを含むｐ型又はｎ型シリ
コン薄膜基板を、弗素、塩素及び水素の群から選
択された元素のガスと、シリコン薄膜基板中の不
純物Ａを異なる不純物Ｂを含むガスとからなる混
合ガスのプラズマ放電状態に晒し、シリコン薄膜
基板の不純物Ａの濃度をシリコン薄膜基板の表面
から所望の深さまで減少させ、と同時に不純物Ｂ
をシリコン薄膜基板に表面から任意の深さまでド
ーピングすることを顕著な特徴とする。 また、不純物Ａが除去されることによつて、で
きたダングリングボンドは弗素又は水素と結合す
ると考えられる。 例えば、ボロン原子を不純物として含むｐ型シ
リコン薄膜表面から、リン原子をドーピングする
ことによつてpn型接合素子を本発明により製造
する場合には、このｐ型シリコン薄膜基板を、ホ
スフインPH3を水素で希釈した混合ガス又は五フ
ツ化リンを弗素で希釈した混合ガスのプラズマ放
電状態下にさらす。この操作によつてｐ型シリコ
ン薄膜基板中のボロン原子の量は表面から所望の
深さまで減少される一方、混合ガス中のリン原子
がシリコン薄膜基板の表面から任意の深さまで、
ドーピングされ、成膜工程を必要とせず、pn接
合素子が作製される。又、リン原子を不純物とし
て含むｎ型アモルフアスシリコン薄膜基板から、
ボロン原子をドーピングすることによつてpn接
合素子を本発明により製造する場合には、このｎ
型シリコン薄膜基板を、ジボランB2H6を水素で
希釈した混合ガス又は三フツ化ボロンを弗素で希
釈した混合ガスのプラズマ放電状態下にさらす。
この操作によつてｎ型シリコン薄膜基板中のリン
原子の量は表面から所望の深さまで減少される一
方、混合ガス中のボロン原子がシリコン薄膜の表
面から任意の深さまで、ドーピングされ、成膜工
程を必要とせず、pn接合素子が作製される。 上記いずれの方法においても、混合ガスの組成
即ち混合割合を変えることによつて、シリコン薄
膜基板からの不純物の減少深さ及び他の不純物の
ドーピング深さを制御することができ、それによ
つて所望の性能を持つた種々のpn接合素子を製
造することができ、更にはpin接合素子をも製造
することができる。更に詳しく説明すると、本発
明に係る製造方法において、混合ガスの組成は放
電時圧力及び時間並びに電力密度と共に本発明に
係る製造方法を実施する際の重要なパラメータで
ある。ガス組成について説明すると、（不純物Ｂ
ガス／弗素又は水素ガス）比が小さいときは、弗
素又は水素によりシリコン薄膜基板中の不純物Ａ
が表面から減少される深さに対して、新しい不純
物Ｂがドーピングされる表面からの深さは浅くな
る。このため製造された素子はpin接合素子とな
る。一方、（不純物Ｂガス／弗素又は水素ガス）
比が大きいときは、弗素又は水素により、シリコ
ン薄膜基板中の不純物Ａが表面から減少される深
さと、新しい不純物Ｂがドーピングされる表面か
らの深さが、ほぼ同じとなる。このため製造され
た素子はpn接合素子となる。本発明の実施に際
し好ましい混合ガス組成はB2H6，BF3／H2又は
PH3，PF5／H2で10-5〜10-1であることが分つ
た。又該混合ガスの真空容器内への流量はプラズ
マ状態を安定に保つように設定されることが必要
であり、0.5〜100SCCMにて好効果が得られた。 本発明に係る製造方法を実際する際の重要なパ
ラメータの一つである放電時圧力は1.5×
10-2Torr〜3Torrに制御されるのが好ましい。つ
まり、放電時圧力が1.5×10-2Torr以下であると
真空容器内の流れが拡散流となりシリコン薄膜基
板より放出された不純物が再びシリコン薄膜基板
へと混入する可能性が大となるために、真空容器
内の流れを粘性流とするべく放電時圧力は1.5×
10-2Torr以上であることが必要となる。又上限
としての放電時圧力3Torrは、電極とアースシー
ルドとの放電を防止するためであり、主に、装置
因子によるものである。又放電電力密度は使用さ
れるプラズマガスの性質により変化するが、0.5
〜50W／cm2が適当である。このような条件下にお
ける放電時間は１秒〜５時間の間で種々に変える
ことができる。又、放電電力密度と放電時間との
関係について言えば、一般に放電電力密度は原始
添加不純物元素の減少深さ及び新たな不純物のド
ーピング深さに関与し、放電時間は原始添加不純
物元素の減少量及び新たな不純物のドーピング量
に関与するということができる。 以上の説明で明らかなように、本発明の主たる
目的は、従来の製造方法に比べて少ない成膜工程
にてpn型又はpin型のシリコン薄膜を製造するこ
とである。 本発明の他の目的は、良好な光電気伝導度及び
暗電気伝導度を有し且つ光エネルギ変換効率の向
上した太陽電池、画像形成用光導電体、読取装置
用光電変換素子又はダイオード等の作製に使用す
ることのできるpn型又はpin型シリコン薄膜の製
造方法を提供することである。 本発明に係る製造方法においては、本発明に従
つて成膜工程を施される原始シリコン薄膜基板と
しては、シリコン単結晶半導体、及びシラン
SiH4にドーバントガスを混合したものを原料ガ
スとしプラズマ雰囲気下にて任意の基板上に成膜
された非晶質のシリコン半導体等のｐ型又はｎ型
シリコン薄膜を使用することができるが、更に本
出願人に係る特許出願（特願昭55−143010号）に
記載されるようなシリコン薄膜、即ち、シラン
SiH4またはハロゲン化シランSiH0〜3X4〜1（Ｘ：ハ
ロゲン元素）のいずれか、またはその２種以上の
混合ガスを原料ガスとし、これにドーバントガス
を混合し、成膜速度を十分に制御し結晶、非品質
混合層を生成する目的で、前記混合ガスを、ヘリ
ウム、ネオン、アルゴン等の希ガスまたは水素等
で約１対１より大きい割合で希釈するとともに、
約0.2W／cm2以上のプラズマ放電電力密度の電力
を投入しながら成膜されたシリコン薄膜をも都合
よく適用し得るものである。 次に、本発明に係るシリコン薄膜の製造方法を
実施例に則して説明する。 実施例 １ 第１図において、混合容器１を含めた全装置系
を油回転ポンプ２および油拡散ポンプ３を使つて
約10-6Torrの真空にし、つぎにフツ素ボンベ４
または水素ボンベ５、さらにドーバントガス（シ
ボラン又はホスフイン）ポンベ６または７よりガ
スを混合容器１に所要の割合で導入し、混合す
る。混合されたガスは流量計８を通して真空容器
９中に一定流量で導入される。メインバルブ１０
で操作して真空容器９中の真空度を真空計を１１
で監視しながら所要の圧力に維持する。真空容器
内の流れの状態は、基板膜中の放出された不純物
の再混入を防止するため、粘性流領域に調整され
る。これば、主に真空容器内圧力を1.5×
10-2Torr以上に維持することによつて実現でき
る。高周波発振器あるいは直流電源１２で電極１
３及び１３′間に高周波電圧を印加してグロー放
電を発生させる。基板１５としては、ｎ型又はｐ
型シリコン薄膜基板を使用する。基板薄膜は0.1
〜1μｍの範囲が好ましいが本実施例では0.7μｍと
した。この基板１５はヒーター１４で加熱された
基台上に記載され、ヒーターで所要の温度に加熱
される。以上の方法によりシリコン薄膜基板１５
はpn接合素子又はpin接合素子となる。 第１表に本発明による製造方法の実施例を示
す。使用したｐ型シリコン薄膜基板の成膜条件
は、SiH4：H2＝１：１の混合ガスを用い、ドー
バントとしてジボランB2H6をSiH4に対して２％
（体積基準）混合したものを原料ガスとして、プ
ラズマ放電電力密度0.1W／cm2、成膜圧力５〜
10-2Torr、原料ガス流量15SCCM、成膜時間60
分としたものであり、ｐ型シリコン基板はITO透
明電極上に上記実施例１に記載の成膜条件で製作
されたものである。 第１表の試料No.１およびNo.２の素子は、Ｖ−ｉ
特性から整流性が確認され、このことからpn接
合素子が作製されたことがわかつた。 更に試料No.２についてEMX測定及び加熱ガス
放出試験を行ない、その結果リン原子がｐ型シリ
コン薄膜中に４原子％含有していることが確認さ
れ、本発明の製造方法によりリン原子がドービン
グされていることが証明された。 The present invention relates to a method for producing a silicon thin film that can be applied to diodes, solar cells, photoconductors for image formation, photoelectric conversion elements for reading devices, and the like. Conventionally, silicon thin films have been used as pin or PN junction devices to achieve the intended purpose. Such a pin or pn junction element is usually formed by forming a p-type silicon thin film doped with B (boron) as an impurity in a plasma atmosphere by a glow discharge method, and then adding an active layer on the p-type silicon thin film. I-type silicon thin film and P
It is produced by two or three film forming steps of growing an n-type silicon thin film doped with (phosphorus) or directly growing the n-type silicon thin film on the p-type silicon thin film. Alternatively, first the n-layer film, then the i-type layer and the p-layer film, or directly on the n-layer film.
The fabrication method for depositing the layers was also carried out in the same manner. However, when a new upper layer is deposited on an already grown lower layer film, impurities from the lower layer (already grown) film are released in a plasma atmosphere, and the elements fabricated using such a film formation method are damaged. It has the disadvantage of contaminating the membrane. As a result, a film grown on a film containing impurities has lower photoelectric conductivity and dark electrical conductivity than a film grown on a substrate that does not contain impurities. For this reason, especially when manufacturing pin junction semiconductor devices intended for solar cells,
Regarding devices fabricated in the order of substrate, p-layer film, i-layer film, and n-layer film, impurities added to the p-layer film are mixed into the i-layer film, so the photoelectric conductivity and dark electrical conductivity are As a result, a good bonding surface is not formed. On the other hand, the substrate, n-layer film, i-layer film, p
Regarding devices manufactured in the order of layers, impurities added to the n-layer film mix into the i-layer film and shift the position of the Fermi level, making it impossible to obtain a sufficient open circuit voltage. In the end, these things
This means that the light energy conversion efficiency decreases, and not only does it degrade the performance of solar cells, but it also causes a decrease in performance when used for various other purposes. The present inventors have prepared a p-type silicon thin film substrate or an n-type silicon thin film substrate doped with an impurity element using fluorine,
When placed under a plasma discharge state of a mixed gas of at least one element selected from the group of chlorine and hydrogen and a gas containing impurities of a different type than the impurities in the silicon thin film substrate, the silicon thin film substrate We found that the amount of impurities at a depth of 5000 Å from the surface decreased, and at the same time, another type of impurity in the mixed gas was doped to any depth from the surface of the silicon thin film substrate. Furthermore, the degree and depth of the reduction of impurities from the silicon thin film substrate, the amount of doping of a new different kind of impurity to the silicon thin film substrate, and the doping depth of the new impurity are determined by the mixture placed in one plasma discharge state. It has been found that various changes can be made by adjusting the gas composition, the pressure and time during plasma discharge in the second vacuum vessel, and the third plasma discharge power density. The present invention has been made based on the above new findings. That is, in the method for manufacturing a silicon thin film according to the present invention, a p-type or n-type silicon thin film substrate containing impurity A is treated with a gas of an element selected from the group of fluorine, chlorine, and hydrogen, and impurity A in the silicon thin film substrate. and a gas containing different impurities B to reduce the concentration of impurity A on the silicon thin film substrate to a desired depth from the surface of the silicon thin film substrate, and at the same time reduce the concentration of impurity A on the silicon thin film substrate to a desired depth from the surface of the silicon thin film substrate.
A distinctive feature is that the silicon thin film substrate is doped from the surface to an arbitrary depth. Further, it is considered that the dangling bonds created by removing impurity A bond with fluorine or hydrogen. For example, when manufacturing a pn-type junction device according to the present invention by doping phosphorus atoms from the surface of a p-type silicon thin film containing boron atoms as an impurity, the p-type silicon thin film substrate is coated with phosphine PH3 . A mixed gas diluted with hydrogen or phosphorus pentafluoride is exposed to a plasma discharge state of a mixed gas diluted with fluorine. By this operation, the amount of boron atoms in the p-type silicon thin film substrate is reduced to a desired depth from the surface, while the amount of phosphorus atoms in the mixed gas is reduced to a desired depth from the surface of the silicon thin film substrate.
A pn junction device is fabricated by doping without the need for a film formation process. In addition, from an n-type amorphous silicon thin film substrate containing phosphorus atoms as an impurity,
When a pn junction device is manufactured according to the invention by doping with boron atoms, this n
The type silicon thin film substrate is exposed to a plasma discharge state of a mixed gas of diborane B 2 H 6 diluted with hydrogen or a mixed gas of boron trifluoride diluted with fluorine.
Through this operation, the amount of phosphorus atoms in the n-type silicon thin film substrate is reduced to a desired depth from the surface, while the boron atoms in the mixed gas are doped to a desired depth from the surface of the silicon thin film, forming a film. A pn junction element is manufactured without the need for any process. In any of the above methods, by changing the composition of the mixed gas, that is, the mixing ratio, the depth of impurity reduction from the silicon thin film substrate and the doping depth of other impurities can be controlled. It is possible to manufacture various pn junction devices with the following performance, and even pin junction devices can be manufactured. To explain in more detail, in the manufacturing method according to the present invention, the composition of the mixed gas is an important parameter when carrying out the manufacturing method according to the present invention, together with the discharge pressure and time and the power density. To explain the gas composition, (Impurity B
When the ratio (gas/fluorine or hydrogen gas) is small, impurity A in the silicon thin film substrate is removed by fluorine or hydrogen.
The depth from the surface to which the new impurity B is doped becomes shallower than the depth from the surface to which the new impurity B is doped. Therefore, the manufactured device becomes a pin junction device. On the other hand, (Impurity B gas/fluorine or hydrogen gas)
When the ratio is large, the depth at which the impurity A in the silicon thin film substrate is reduced from the surface by fluorine or hydrogen is approximately the same as the depth from the surface at which new impurity B is doped. Therefore, the manufactured device becomes a pn junction device. Preferred mixed gas compositions for carrying out the present invention are B 2 H 6 , BF 3 /H 2 or
It was found that PH 3 and PF 5 /H 2 were 10 -5 to 10 -1 . Further, the flow rate of the mixed gas into the vacuum container must be set to keep the plasma state stable, and good effects were obtained at 0.5 to 100 SCCM. The discharge pressure, which is one of the important parameters when actually implementing the manufacturing method according to the present invention, is 1.5×
It is preferably controlled to between 10 −2 Torr and 3 Torr. In other words, if the discharge pressure is 1.5×10 -2 Torr or less, the flow inside the vacuum container becomes a diffusion flow, and there is a high possibility that impurities released from the silicon thin film substrate will mix into the silicon thin film substrate again. , the pressure during discharge is 1.5× to make the flow inside the vacuum container a viscous flow.
It needs to be 10 -2 Torr or higher. The upper limit of the discharge pressure of 3 Torr is to prevent discharge between the electrode and the earth shield, and is mainly due to equipment factors. Also, the discharge power density varies depending on the properties of the plasma gas used, but it is 0.5
~50W/ cm2 is appropriate. The discharge time under such conditions can be varied between 1 second and 5 hours. Regarding the relationship between discharge power density and discharge time, generally speaking, discharge power density is related to the depth of reduction of originally added impurity elements and the doping depth of new impurities, and discharge time is related to the amount of reduction of originally added impurity elements. It can be said that it is related to the doping amount of new impurities. As is clear from the above description, the main purpose of the present invention is to manufacture a pn type or pin type silicon thin film using fewer film forming steps than conventional manufacturing methods. Another object of the present invention is to provide solar cells, image forming photoconductors, photoelectric conversion elements or diodes for reading devices, etc., which have good photoelectric conductivity and dark electric conductivity and have improved light energy conversion efficiency. An object of the present invention is to provide a method for manufacturing a pn type or pin type silicon thin film that can be used for manufacturing. In the manufacturing method according to the present invention, the original silicon thin film substrate subjected to the film forming process according to the present invention is a silicon single crystal semiconductor and a silane single crystal semiconductor.
A p-type or n-type silicon thin film such as an amorphous silicon semiconductor formed on an arbitrary substrate in a plasma atmosphere using a mixture of SiH 4 and a dopant gas as a raw material gas can be used. A silicon thin film, that is, a silane film as described in the patent application filed by the present applicant (Japanese Patent Application No. 143010/1983)
SiH 4 or halogenated silane SiH 0~ 3 diluting the gas mixture with a rare gas such as helium, neon, argon, or hydrogen in a ratio greater than about 1:1 for the purpose of producing a controlled crystalline, non-quality mixed layer;
A silicon thin film formed while applying power with a plasma discharge power density of about 0.2 W/cm 2 or more can also be conveniently applied. Next, a method for manufacturing a silicon thin film according to the present invention will be explained based on examples. Example 1 In FIG. 1, the entire system including the mixing container 1 is brought to a vacuum of approximately 10 -6 Torr using the oil rotary pump 2 and the oil diffusion pump 3, and then the fluorine cylinder 4 is vacuumed.
Alternatively, gases are introduced into the mixing container 1 at a required ratio from a hydrogen cylinder 5 and a dopant gas (ciborane or phosphine) cylinder 6 or 7 and mixed. The mixed gas is introduced into the vacuum vessel 9 through the flow meter 8 at a constant flow rate. Main valve 10
The degree of vacuum in the vacuum container 9 can be determined using the vacuum gauge 11.
Maintain the required pressure while monitoring. The flow conditions within the vacuum vessel are adjusted to the viscous flow regime to prevent re-entrainment of released impurities in the substrate film. This will mainly increase the pressure inside the vacuum container by 1.5×
This can be achieved by maintaining the temperature at 10 -2 Torr or higher. Electrode 1 with high frequency oscillator or DC power supply 12
A high frequency voltage is applied between 3 and 13' to generate glow discharge. The substrate 15 may be n-type or p-type.
A silicon thin film substrate is used. Substrate thin film is 0.1
A range of 1 μm to 1 μm is preferable, but in this example, it was set to 0.7 μm. This substrate 15 is placed on a base heated by a heater 14, and heated to a required temperature by the heater. By the above method, the silicon thin film substrate 15
becomes a pn junction element or a pin junction element. Table 1 shows examples of the manufacturing method according to the present invention. The p-type silicon thin film substrate used was formed using a mixed gas of SiH 4 :H 2 = 1:1, with diborane B 2 H 6 as a dopant at 2% relative to SiH 4.
(Volume basis) Using the mixture as a source gas, plasma discharge power density 0.1W/cm 2 , film forming pressure 5~
10 -2 Torr, raw material gas flow rate 15SCCM, film formation time 60
The p-type silicon substrate was fabricated on an ITO transparent electrode under the film-forming conditions described in Example 1 above. The elements of samples No. 1 and No. 2 in Table 1 are V-i
Rectifying properties were confirmed from the characteristics, and this revealed that a pn junction element had been fabricated. Furthermore, EMX measurements and heating gas release tests were performed on sample No. 2, and the results confirmed that 4 at.% of phosphorus atoms were contained in the p-type silicon thin film, indicating that phosphorus atoms were doped by the manufacturing method of the present invention. It has been proven that

【表】 第２図は、本発明に従つた製造方法により作製
された薄膜の電気伝導度をプラズマ放電時間の関
数として示すものである。ただし、第２図に示さ
れるシリコン薄膜は、本発明の製造方法によりｐ
型薄膜基板の表面からボロン原子量が減少するこ
とを確認するためにプラズマ中にホスフインガス
を混合していない条件により整造されている。す
なわち、第２図に示される試料の製造方法は、ボ
ロンドーピングｐ型シリコン薄膜を、水素流量
10SCCM、放電時圧力1Torr、電力密度0.8W／
cm2、基板温度300℃、の下で水素プラズマ放電す
ることによるものである。第２図から、放電時間
とともに電気伝導度が減少することがわかる。こ
れは、ｐ型シリコン薄膜表面からの任意の深さま
で、ボロン原子量が減少するためである。 実施例 ２ 実施例１と同様の方法において、ポロンドープ
ｐ型アモルフアスシリコン薄膜基板（厚み5000
Å）をPH3ガスと水素ガスの混合ガスのプラズマ
雰囲気下で処理し、pin接合素子を作製した。該
接合素子はＶ−ｉ特性からpin接合素子であるこ
とが確認された。又、第３図はSIMSの測定結果
を表わすものであるが、この第３図からも、基板
膜中のボロンが表面から3500の深さまで減少して
おり、混合ガス中のリンが新たにドーピングされ
ていることが理解されるであろう。 以上説明のように、本発明の製造方法によれば
ｐ型またはｎ型シリコン薄膜基板の表面から任意
の深さまで不純物量を減少させ、と同時に新たな
不純物をこのシリコン薄膜中にドーピングするこ
とができる。従つて、本発明の製造方法は成膜工
程を従来の方法に比べ減少させて、pn型接合素
子又はpin型接合素子を製造することができ製造
工程を単純化し、シリコン半導体の生産性を増大
せしめると共に、性能の良いダイオード、太陽電
池等を作ることができるといつた効果を有する。TABLE FIG. 2 shows the electrical conductivity of thin films produced by the production method according to the invention as a function of plasma discharge time. However, the silicon thin film shown in FIG.
In order to confirm that the amount of boron atoms is reduced from the surface of the type thin film substrate, it was prepared under conditions where no phosphine gas was mixed in the plasma. That is, the method for manufacturing the sample shown in FIG.
10SCCM, discharge pressure 1Torr, power density 0.8W/
cm 2 and a substrate temperature of 300° C. by hydrogen plasma discharge. From FIG. 2, it can be seen that the electrical conductivity decreases with discharge time. This is because the boron atomic weight decreases to an arbitrary depth from the surface of the p-type silicon thin film. Example 2 In the same method as in Example 1, a poron-doped p-type amorphous silicon thin film substrate (thickness 5000 mm
) was processed in a plasma atmosphere of a mixed gas of PH3 gas and hydrogen gas to fabricate a pin junction device. The junction element was confirmed to be a pin junction element from the Vi characteristics. Also, Figure 3 shows the SIMS measurement results, and it can be seen that boron in the substrate film has decreased to a depth of 3500 mm from the surface, and phosphorus in the mixed gas has been newly doped. It will be understood that what is being done. As explained above, according to the manufacturing method of the present invention, it is possible to reduce the amount of impurities from the surface of a p-type or n-type silicon thin film substrate to an arbitrary depth, and at the same time, dope new impurities into this silicon thin film. can. Therefore, the manufacturing method of the present invention can manufacture pn-type junction devices or pin-type junction devices by reducing the number of film-forming steps compared to conventional methods, simplifying the manufacturing process and increasing the productivity of silicon semiconductors. In addition, it has the effect of making it possible to make diodes, solar cells, etc. with good performance.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明に係るシリコン薄膜製造方法を
実施する装置を示す概略図である。第２図は本発
明に係る製造方法により作製されたシリコン薄膜
の電気伝導度をプラズマ放電時間の関数として示
すグラフである。第３図は本発明に係る製造方法
により作製されたシリコン薄膜のSIMSの測定結
果を示すグラフである。 １：混合容器、４，５，６，７：ガスボンベ、
９：真空容器、１３，１３′：電極、１５：基板。 FIG. 1 is a schematic diagram showing an apparatus for implementing the silicon thin film manufacturing method according to the present invention. FIG. 2 is a graph showing the electrical conductivity of a silicon thin film produced by the production method according to the present invention as a function of plasma discharge time. FIG. 3 is a graph showing SIMS measurement results of a silicon thin film manufactured by the manufacturing method according to the present invention. 1: Mixing container, 4, 5, 6, 7: Gas cylinder,
9: Vacuum container, 13, 13': Electrode, 15: Substrate.

Claims (1)

【特許請求の範囲】 １ 一の不純物元素がドープピングされたシリコ
ン薄膜基板を弗素、塩素及び水素の群から選択さ
れた少なくとも一元素のガスと、前記シリコン薄
膜基板中前記原始添加不純物とは別種の不純物元
素を含むガスとから成る混合ガスのプラズマ雰囲
気下に置き、該プラズマ雰囲気の圧力を1.5×
10-2Torr〜3Torrの範囲に設定して反応帯域に粘
性流領域を形成させ、電力密度を0.5W／cm2〜
50W／cm2の範囲に設定し、更に前記混合ガス中一
元素ガスに対する不純物元素ガスの割合を10-5〜
10-1の範囲で変更することにより、前記シリコン
薄膜の表面から最大5000Åの深さにわたつて該シ
リコン薄膜基板中の原始添加不純物量を減少させ
ると同時にプラズマ中の新たな不純物のドーピン
グ深さを制御することを特徴とする、pn型接合
又はpin型接合を有するシリコン薄膜の製造方法。 ２ シリコン薄膜は、単結晶のシリコン半導体で
ある特許請求の範囲第１項記載の製造方法。 ３ シリコン薄膜は、非晶質のシリコン半導体で
ある特許請求の範囲第１項記載の製造方法。 ４ シリコン薄膜は非晶質層中に微結晶粒が混在
しているシリコン半導体である特許請求の範囲第
１項記載の製造方法。[Scope of Claims] 1. A silicon thin film substrate doped with one impurity element is treated with a gas of at least one element selected from the group of fluorine, chlorine, and hydrogen, and a type of impurity different from the originally added impurity in the silicon thin film substrate. Place in a plasma atmosphere of a mixed gas consisting of a gas containing impurity elements, and increase the pressure of the plasma atmosphere to 1.5
10 -2 Torr to 3 Torr to form a viscous flow region in the reaction zone, and the power density to 0.5 W/cm 2 to
The ratio of the impurity element gas to the single element gas in the mixed gas is set to 10 -5 to 50 W/cm 2 .
By changing the doping depth within the range of 10 -1 , the amount of originally added impurities in the silicon thin film substrate is reduced over a maximum depth of 5000 Å from the surface of the silicon thin film, and at the same time, the doping depth of new impurities in the plasma is increased. 1. A method for producing a silicon thin film having a pn-type junction or a pin-type junction, the method comprising controlling the . 2. The manufacturing method according to claim 1, wherein the silicon thin film is a single crystal silicon semiconductor. 3. The manufacturing method according to claim 1, wherein the silicon thin film is an amorphous silicon semiconductor. 4. The manufacturing method according to claim 1, wherein the silicon thin film is a silicon semiconductor in which microcrystalline grains are mixed in an amorphous layer.
JP56105704A 1981-07-08 1981-07-08 Manufacture of silicon thin-film Granted JPS589321A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP56105704A JPS589321A (en) 1981-07-08 1981-07-08 Manufacture of silicon thin-film
US06/394,074 US4490208A (en) 1981-07-08 1982-07-01 Method of producing thin films of silicon
DE8282303526T DE3276280D1 (en) 1981-07-08 1982-07-05 Method of producing thin films of silicon
EP82303526A EP0069580B1 (en) 1981-07-08 1982-07-05 Method of producing thin films of silicon
US06/790,781 US4598304A (en) 1981-07-08 1985-10-23 Thin film devices of silicon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56105704A JPS589321A (en) 1981-07-08 1981-07-08 Manufacture of silicon thin-film

Publications (2)

Publication Number Publication Date
JPS589321A JPS589321A (en) 1983-01-19
JPH0376019B2 true JPH0376019B2 (en) 1991-12-04

Family

ID=14414741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56105704A Granted JPS589321A (en) 1981-07-08 1981-07-08 Manufacture of silicon thin-film

Country Status (1)

Country Link
JP (1) JPS589321A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2744680B2 (en) * 1990-06-21 1998-04-28 株式会社富士電機総合研究所 Manufacturing method of thin film solar cell
JP4852125B2 (en) * 2009-06-19 2012-01-11 株式会社トーモク Packaging box

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55151374A (en) * 1979-05-14 1980-11-25 Shunpei Yamazaki Semiconductor device

Also Published As

Publication number Publication date
JPS589321A (en) 1983-01-19

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