JPH0376495B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an interrupt control device for a microcomputer or the like, and more particularly to an interrupt control device that has programmable priorities and is capable of multiple processing of all interrupt requests.

(Prior art) Interrupt control refers to the central processing unit (hereinafter referred to as
It's called a "CPU." ) is a control for temporarily suspending program execution in response to a processing request asynchronously generated from peripheral hardware during program execution, and starting execution of the program in response to the processing request. There are various types of interrupt factors in a microcomputer system, and each interrupt factor has a priority depending on its importance in the application. When a new interrupt request occurs while a certain interrupt process is being executed, the process of interrupting the currently executing interrupt process and executing the process in response to the new interrupt request is called multiprocessing. Multiprocessing is performed when an interrupt request of an interrupt factor having a higher priority than that of the interrupt factor of the interrupt process being executed occurs.

By the way, in conventional interrupt control devices, the generation source of each interrupt request (hereinafter referred to as "interrupt generation source")
The priority was fixed. For this reason,
It was not possible to perform control that optimally corresponds to the processing priority of each interrupt factor, which varies depending on the application.

For example, assume that the interrupt priority of a timer is fixed to be higher than that of a serial input/output device. In this setting, this priority order is suitable for a system in which a timer sends a signal at a certain set time interval to control peripheral devices in real time. However, in systems where it is important to control peripheral devices using input from the keyboard, if a timer is also used, data input interrupt processing requests from serial input/output devices may be postponed, and this interrupt priority is Not fit for purpose of the system. In other words, with conventional interrupt control devices in which the priority order is fixed for each interrupt source, it is impossible to perform priority control of interrupt requests that is optimal for the importance of each interrupt source, which differs depending on the application. There were flaws.

In addition, with conventional interrupt control devices, when performing multiple processing, it is necessary to prohibit complicated interrupt reception (hereinafter referred to as "mask").
That's what it means. ) required processing. In order to accept multiple interrupt requests with higher priority levels while a certain interrupt process is being executed, the interrupt service program must mask lower level interrupts. However, with this method, the mask is set every time the interrupt service program starts execution, and when entering multiple interrupt processing, the mask state is saved and the mask is changed, and when returning from multiple interrupt processing, the mask state is saved and changed. We have to go through the process of putting masks back on. As a result, the execution speed of the process is slow, and the program has to describe operations other than the original interrupt processing operation, resulting in a very complicated process.

Furthermore, conventional interrupt control devices require complicated software procedures when performing multiple processing of the same interrupt request.

FIG. 1 is a block diagram showing the system configuration of an example of a conventional interrupt control device that performs multiple processing of the same interrupt request. In this conventional example, when an interrupt control device with a limited number of input terminals handles a large number of interrupt requests, a dependent interrupt controller is used to combine requests from multiple interrupt sources into one and send it to the interrupt control device. This is for inputting data.

In FIG. 1, an interrupt control device 21 directly controls interrupt sources a, b, and c, and interrupt sources d-
1, d-2, d-3, and d-4 are connected to and controlled by a dependent interrupt controller 22. From the perspective of the interrupt control device 21, the interrupt sources d-1, d-
2, d-3, and d-4 appear as one interrupt source d. The dependent interrupt controller 22 performs priority control on the interrupt sources d-1, d-2, d-3, and d-4, and outputs an interrupt request 14. For example, if an interrupt request from interrupt source d-2, which has a higher priority, occurs while an interrupt process is being executed based on a request from interrupt source d-3, the dependent interrupt controller 22
4, and upon receiving it, the interrupt control device 21
performs multiple processing of the same interrupt request for interrupt source d. The CPU 20 executes the interrupt service program for the interrupt source d, detects the occurrence of an interrupt request for the interrupt source d-2, branches to the interrupt service program for the interrupt source d-2, and executes processing. When the processing of the interrupt request from the interrupt source d-2 is completed, the process returns to the service program for the interrupt source d.

Here, if the degree of overlap of interrupt processing for interrupt source d is not known, the mask that was saved at the end of the service program for interrupt source d will be restored, and subsequent priority control will not be normal. become unable. In other words, in order to properly control the priority of interrupts, it is necessary to remember the degree of duplication of the same interrupt.

However, in conventional interrupt processing, a software counter must be provided to maintain the degree of duplication of the same interrupt, and the counter is counted up at the beginning of the interrupt service program, counted down at the end, and the interrupt is masked according to the result. I had to go through the procedure of operating the In other words, multiple processing of the same interrupt request has the disadvantage that, in addition to the above-mentioned masking operation, a more complicated operation must be performed.

(Objective of the Invention) The object of the present invention is to eliminate the above-mentioned drawbacks, to make it possible to arbitrarily set the priority order of interrupt requests, to eliminate the need for complicated procedures even in multiple interrupt processing, and to be able to handle different interrupt requests. It is an object of the present invention to provide an interrupt control device which can easily handle multiple processing of a large number of interrupt requests and multiple processing of the same interrupt request in a unified manner.

(Structure of the Invention) The interrupt control device of the present invention includes an interrupt request storage means for storing interrupt requests for each interrupt generation source, a priority specifying means for specifying a processing priority for each interrupt request, and a priority specifying means for specifying a processing priority for each interrupt request. scanning signal generating means for outputting a scanning signal to be scanned from the input terminal; comparing means for comparing the scanning signal with the contents of the priority order specifying means; reception number holding means for storing the number of accepted interrupts for each priority; index signal output means for outputting an index signal indicative of the priority of an interrupt; the scanning signal output means repeatedly outputs the scanning signal at a predetermined period; and the comparison means outputs the scanning signal and the contents of the priority order means. and detection control means for performing priority control based on the index signal and the contents of the interrupt request storage means and controlling the information held in the acceptance number holding means when a match is detected.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of one embodiment of the present invention.

In this embodiment, interrupt request storage units 107-A to 107-A store interrupt requests for each interrupt generation source A to D.
107-D, and priority designation units 105-A to 105-D that designate processing priority for each interrupt request.
and a scanning signal 102 that scans from the highest priority order.
A control unit A10 serving as a scanning signal generating means for outputting
1, a scanning signal 102, and a priority designation unit 105-
Detection units 104-A to 104-D as comparison means for comparing the contents of A to 105-D, and an acceptance number holding unit 117 that stores the number of accepted interrupts for each priority.
, a control section B101' as an index signal output means that outputs a peer signal 118 as an index signal indicating the priority of the interrupt currently being accepted, and a control section A101 that repeatedly outputs the scanning signal 102 at a predetermined period for detection. Units 104-A to 104-D output the scanning signal 102 and priority designation units 105-A to 105-.
If a match with the contents of D is detected, the peer signal 118
and selection units 115-A to 115-D as detection control means that perform priority control and control of the information held in the acceptance number holding unit 117 based on the contents of the interrupt request storage units 107-A to 107-D and interrupt acceptance. Part 1
08-A to 108-D. Note that 106-A to 106-D are interrupt request control units, and furthermore, the control unit A101 and the control unit B101' are configured as one block here.

This embodiment shows the case where there are four types of interrupt sources A, B, C, and D, and the subscripts A, B, C, and D of the numbers in the figure represent the interrupt sources A, B, C, and D, respectively.
Indicates that this is a part involved in processing interrupt requests from B, C, and D. The parts surrounded by broken lines in FIG. 2 that are involved in processing interrupt requests from the respective interrupt sources have exactly the same configuration. Hereinafter, a section that processes interrupt requests from each interrupt source will be explained first, and then a section that controls the entire interrupt control device based on the processing results for each interrupt source will be explained.

The scanning signal 102 is “0”, “1”, “2”, “3”
，
This is a signal that repeatedly scans the priority order from the highest priority order, such as "0", "1", "2", . . . . The peer signal 118 is a signal that is output only during the period when the scanning signal 102 becomes equal to the priority of the interrupt currently being accepted by the interrupt control device. Figure 3 a~
The timing chart for e shows that the interrupt priority is 4.
An example of the output of the scanning signal 102 and the same level signal 118 is shown together with the highest level signal 119 when the level is assumed to be the same level. a, b, c, d, e in the same figure
If no interrupts are accepted,
This shows a case where interrupts with priorities 3, 2, 1, and 0 are accepted.

Hereinafter, a portion that processes an interrupt request from interrupt source A will be explained as an example. The interrupt request storage unit 107-A holds the interrupt request 100-A from the interrupt source A.
- Set when A is input, interrupt acceptance signal 1
It is reset when both 10-A and interrupt confirmation signal 314 are input. Interrupt request control unit 106-A
holds whether to permit or prohibit acceptance of interrupt requests from interrupt source A (hereinafter referred to as "A's interrupt requests"), and can be set by a program. The priority designation unit 105-A holds the interrupt priority of the interrupt request from the interrupt source A, and can be set by a program. The detection unit 104-A receives the scanning signal 102
and the contents of the priority order written in the priority order specifying section 105-A, and if a match is detected, a match signal 109-A is output. The selection unit 115-A controls the output of the selected coincidence signal 116-A in synchronization with the input of the coincidence signal 109-A.
The selection unit 115-A includes permission to output the selected coincidence signal 116-A when the peer signal 118 is output;
Prohibition can be set programmatically. The selection unit 115-A outputs the selected match signal 116-A in synchronization with the input of the match signal 109-A whenever the peer signal 118 is not input. Peer signal 1
18 is input, the selection unit 115-A selects the coincidence signal 10 according to the permission/prohibition setting described above.
Enables or prohibits output of the selection match signal 116-A when 9-A is input. FIG. 4 shows permission and prohibition information set in the selection unit 115-A and the match signal 109.
-A shows the relationship between the output of the selected match signal 116-A and the input of the peer signal 118. In addition, in the same figure, it is shown that X may be either 1 or 0.

The interrupt reception unit 108-A receives the selection match signal 116-A when the interrupt request storage unit 107-A is set and the interrupt request control unit 106-A holds permission to accept the interrupt request. If input, an interrupt acceptance signal 110-A is output.

The parts corresponding to interrupt sources B, C, and D also function in exactly the same way to process interrupt requests from each interrupt source.

Next, the portion that controls the entire interrupt control device based on the processing information from each of the interrupt sources described above will be explained.

The highest level signal 119 indicates the priority of the highest level of interrupts currently being accepted, and the interrupt end signal 113 indicates that the service program for one interrupt request has been completed.

The control unit A101 receives an interrupt acceptance signal 110-
It controls the output of the scanning signal 102, the same level signal 118, and the interrupt signal 103 using A, B, C, and D, the highest level signal 119, and the interrupt end signal 113 as input information. The control unit A 101 outputs an interrupt signal 103 to the CPU 300 and the acceptance number holding unit 117 when any one of the interrupt acceptance signals 110 -A, B, C, and D is input. The control unit A101 changes the scanning signal 102 from the one with the highest priority to the one with the lowest priority one by one. As shown in FIG. 3a, if the highest priority signal 119 is not output because no interrupt is currently being accepted, the control unit A101 will control the signal at the next timing after the scanning signal 102 becomes the lowest priority. , again sets the scanning signal 102 to the highest priority and continues scanning. Currently accepting interrupts and the highest signal 1
19 is outputting its priority, the third
As shown in Figures b, c, d, and e, the control unit A101
At the next timing when the scanning signal 102 becomes equal to the priority indicated by the highest signal 119, the scanning signal 102 is made the highest priority again and scanning is continued.

As shown in Fig. 3 b, c, d, e, the control unit B
101' indicates that the scanning signal 102 is the highest signal 119
When the priority level becomes equal to the priority level indicated by
Outputs 18.

The reception number holding unit 117 receives the scanning signal 102, the interrupt signal 103, and the interrupt end signal 113 as input information, and is in charge of outputting the highest signal 119. The number of accepted interrupts holding unit 117 holds the number of accepted interrupts for each priority level of all interrupts from the highest to the lowest level. When the interrupt signal 103 is input, the reception number holding unit 117 adds 1 to the number of priority interrupt receptions output to the scanning signal 102 at that time. For example, interrupt signal 103
If the scanning signal 102 is "3" at the time of input, 1 is added to the number of receptions with priority level 3. Reception number holding section 1
17, when the interrupt end signal 113 is input, among those whose number of interrupts accepted is not "0" at that time,
Subtract 1 from the number of receptions for the one with the highest priority. For example, the number of accepted interrupts with priorities 0, 1, 2, and 3 is "1", "0", "3", and "1", respectively.
If so, subtract 1 from the number of receptions with priority 0,
The acceptance numbers are set to "0", "0", "3", and "1", respectively. The number of receptions holding unit 117 indicates that the number of receptions is “0”.
The highest interrupt priority among those that are not available is output as the highest priority signal 119. For example, if the number of accepted interrupts for priorities 0, 1, 2, and 3 is "0", "1", "2", and "0", respectively, then the highest level signal 1
19 is “1”, “0”, “0”, “0”, “1”
Then, the highest signal 119 is "3". If the number of accepted interrupts for all priority levels is "0", the highest level signal 119 is not output.

When the interrupt signal 103 is input, the CPU 300 outputs an interrupt confirmation signal 314 and starts interrupt processing operation. The CPU 300 outputs an interrupt end signal 113 when the execution of the interrupt service program is completed.

Next, the operation of this embodiment will be explained. Fifth
The figure is a timing chart showing a first example of operation of this embodiment. Further, FIG. 6 is a timing chart showing a second example of operation of this embodiment. signal 1
02,109-A,B,C,D,116-B,
C, 118, 110-A, B, C, D, 103,
314, 113, and 119 correspond to the signals with the same numbers in FIG. 2, respectively. 107-B and 107-C indicate the states of the interrupt request storage sections 107-B and 107-C shown in FIG. 2, respectively; "1" indicates a set state, and "0" indicates a reset state. The acceptance count holding unit 117 holds the acceptance counts of interrupts with priorities 0, 1, 2, and 3 at 117-0, 1, 2, and 3, respectively. However, the priorities are set in the order of 0, 1, 2, and 3.

First, an example of multiprocessing operations between different interrupt factors in this embodiment will be explained with reference to FIGS. 2 and 5. First, each priority specifying unit 105-A to 105-A to 10-10
Write the priority in 5-D. In this example, the priority designation section 105-A is 0, and 105-A is 0.
-B has 1, 105-C has 2, 105-D
It is assumed that 3 is written in . In addition, using a signal controlled by a program in the selection units 115-A to 115-D, it is written whether to permit or prohibit the output of the selection coincidence signal 116 when the peer signal 118 is output. Now, selection section 115-A, B,
Assume that output prohibition is written in both C and D. When there is no interrupt request, when the scanning signal 102 changes to 0, 1, 2, 3, the coincidence signal 109-
A, B, C, and D each change like the period P in FIG.

Now, assume that an interrupt request is generated from the interrupt source C at timing _T1 , and that the interrupt is permitted in the interrupt request control unit 106-C. When the scanning signal 102 becomes " ₂ " at timing T2 and the match signal 109-C is output, the selected match signal 116-C is output since the same level signal 118 is not output. As a result, the interrupt is accepted and the interrupt acceptance signal 110-C is output at timing _T2 .
Interrupt signal 1 is sent from the control unit A101 to the CPU 300.
03 is sent. At this time, the reception number holding unit 117
stores the number of receptions for interrupt priority 2 as "1" as stored data 117-2. The interrupt request storage section 107-C is reset by the output of the interrupt confirmation signal 314. interrupt is accepted
While the CPU 300 is executing interrupt processing with priority level 2, when the scanning signal 102 becomes equal to the highest level signal 119 outputting "2", it returns to 0 again as shown at timing _T3 , and the priority level is 0. ,1,
Output only 2. On the other hand, the same level signal 118 is output in synchronization with the scanning signal 102 at timing _T3 when the scanning signal 102 becomes equal to the highest level signal 119. As a result, interrupts with priority levels 0 and 1 can be accepted, but selection units 115-A, B, C,
Since the setting of D prohibits the output of the selected match signals 116-A, B, C, and D when the peer signal 118 is output, the interrupt of priority level 2 is not accepted.

Next, suppose that a higher priority interrupt request is generated from interrupt source B at timing _T4 . Since the priority of interrupt source B is set to 1, when the scanning signal 102 becomes "1", the coincidence signal 109-
B is output, and the selection match signal 116-B is also output. If interrupts from interrupt source B are enabled, interrupt acceptance signal 11 is generated at timing _T5 .
0-B is output, the interrupt is accepted, and the CPU
An interrupt signal 103 is sent to 300. At the same time, the acceptance number holding unit 117 stores the number of interrupt acceptances of interrupt priority 1 as "1" in the storage data 117-1. When the scanning signal 102 becomes "1", the same level signal 118 is output, and at timing _T6 , the scanning signal 10 is output.
2 returns to 0 again. The scanning signal 102 scans only 0 and 1, and the selection units 115-A, B, C, and D each select the selected coincidence signal 11 when the same level signal 118 is output.
6-Since the output of A, B, C, and D is prohibited,
Only interrupts with priority level 0 can be accepted.

Multiple interrupt processing is completed and at timing T ₇
When the interrupt end signal 113 is sent from the CPU 300, the reception number holding unit 117 sets the number of receptions for the highest priority 1 whose reception number is not "0" at that time to 0, and as a result, the highest priority signal 119 changes from "1" to "2", and the scanning signal 102 becomes 0,
It will change from 1 to 2. As a result, it becomes possible to accept interrupts with priority levels 0 and 1 again.

The interrupt processing from interrupt source C is also completed, and at timing _T8 , the CPU 300 sends an interrupt end signal 1.
13 is sent, the number of receptions for all priority orders in the reception number holding unit 117 becomes 0, and the highest level signal 119 is no longer output. The scanning signal 102 outputs priorities as 0, 1, 2, and 3, and the peer signal 118
will no longer be output, returning to the initial state in which all interrupts can be accepted.

Next, an example of the operation of multiple processing of the same interrupt factor will be described with reference to FIGS. 2 and 6. In this embodiment, processing for accepting an interrupt from interrupt source B again during interrupt processing from interrupt source B will be described. Priority order designation units 105-A to 105
-D uses a signal controlled by the program to write the priority order. Now, the priority specification section 105-
Assume that 0 is written to A, 1 is written to 105-B, 2 is written to 105-C, and 3 is written to 105-D. In addition, selection units 115-A, 115-C, and 11
It is assumed that "prohibition" of the output of the selection coincidence signal when the peer signal 118 is output is written in 5-D, and "permission" is written in the selection section 115-B.

At timing _T51 , there is an interrupt request from the interrupt source C, and at that time, the interrupt request specifying section 106-C
Assume that the interrupt is permitted in . When the scanning signal 102 becomes "2" at timing _T52 and a coincidence signal 109-C is generated, the same level signal 118 is generated.
is not output, so the selection match signal 116-C
occurs. As a result, the interrupt is accepted and the interrupt signal 110-C is output, and the control unit A101
An interrupt signal 103 is sent from the CPU 300 to the CPU 300 .
At this time, the reception number holding unit 117 stores the stored data 1
The number of receptions of interrupt priority 2 is stored as "1" as 17-2. The interrupt is accepted and the CPU
While interrupt processing 300 is executing priority 2, the scanning signal 102 outputs only priorities 0, 1, and 2. Also, the peer signal 118 is the scanning signal 1
02 is output synchronously when it has priority 2.

Now, suppose that an interrupt request with priority level 2 occurs again from interrupt source C at timing _T53 . At this time, the match signal 109-C is generated at timing _T54 , but since the "prohibited" state has been written in the selection section 115-C in advance, the selected match signal 116-C is generated by the output of the peer signal 118. No output. Therefore, the interrupt request from interrupt source C that occurs again is not accepted during the interrupt request processing, and the interrupt request storage section 107-C remains set.

Next, assume that a high priority interrupt request occurs from interrupt source B at timing _T55 . The interrupt request storage unit 107-B is set, and at timing _T56 when the scanning signal 102 becomes 1, a coincidence signal 109-B is generated.
occurs and the same-level signal 118 is not output, so the selection match signal 116-B is output. If interrupts from interrupt source B were enabled,
The interrupt is accepted, the interrupt signal 110-B is output, and as a result, the interrupt signal 10 is sent to the CPU 300.
3 is sent, and the reception number holding unit 117 stores the number of receptions for interrupt priority 1 as "1" as stored data 117-1. The scanning signal 102 scans only 0's and 1's, and in synchronization with the scanning signal 102 outputting priority 1, a peer signal 118 is output. During this time, the CPU 300 is processing the interrupt with interrupt priority 1.

Now, suppose that an interrupt with priority 1 is generated again from interrupt request source B at timing _T57 during processing of an interrupt with priority 1. Scanning signal 102
At the timing _T58 when becomes 1, the coincidence signal 116-B
outputs. Since the selection unit 115-B holds the "permitted" state in advance, the match signal 1
At timing _T58 when 09-B outputs and the same level signal 118 outputs, the selection match signal 116
-B outputs. Since the interrupt request storage unit 107-B is set and interrupts from interrupt source B are permitted, the interrupt is accepted at the same timing _T58 , and as a result, the CPU 300 receives the interrupt signal 1.
03 is sent. At the same time, the reception number holding unit 117
As data 117-1, 1 is added to the number of interrupts accepted for priority 1 and stored as "2". Since the highest level signal 119 continues to output the priority level "1", the scanning signal 102 repeatedly outputs the priority level 0 and 1, and the same level signal 118 outputs the priority level "1".
Output synchronously when . The CPU 300 processes multiple interrupt requests with priority level 1.

When the multiple interrupt processing with the same priority is completed and the interrupt end signal 113 is sent from the CPU 300 at timing _T59 , the reception number holding unit 11
7 is set to "1" by subtracting 1 from the number of interrupts accepted for priority 1. Since the highest level signal 119 continues to output priority 1, the scanning signal 102 continues to output priority 0 and 1. At timing T ₆₀ , when the priority level 1 interrupt processing for which the request occurred at timing T ₅₅ is completed and the interrupt end signal 113 is output from the CPU 300, the reception number holding unit 117
is data 1 that holds the number of interrupts accepted with priority 1
17-1 is subtracted by 1 to become "0". Highest signal 1
19 becomes "2", and the scanning signal 102 becomes 0, 1,
It will change to 2. The CPU 300 returns to the priority level 2 interrupt processing that was started at timing _T52 .

The CPU 300 finishes the above-mentioned priority level 2 interrupt processing and sends the interrupt end signal 113 at timing _T61 .
When this is output, the number of receptions for priority 2 interrupts in the reception number holding unit is decreased by 1 to "0". As a result,
The highest signal 119 is not output, and the scanning signal 102
outputs priorities 0, 1, 2, 3, and the peer signal 1
18 does not output, so all interrupts can be accepted.

Since the interrupt request storage unit 107-C is set, when the match signal 109-C is output at timing _T62 and the selection match signal 116-C is output, the interrupt request generated at timing _T53 is accepted. An interrupt acceptance signal 110-C is output. As a result, the interrupt signal 103 is output, and the number of receptions for priority 2 in the reception number holding unit 117 becomes "1". The CPU 300 moves to execution of the priority level 2 interrupt process.

7, 8 and 9 are partial detailed circuit diagrams of the embodiment of FIG. 2, respectively.

FIG. 7 shows the detection unit 104-A, priority order designation unit 105-A, and interrupt request control unit 106-A in FIG.
FIG. 2A is a circuit diagram of an example of an interrupt request storage section 107-A, an interrupt reception section 108-A, and a selection section 115-A.

R.S flip-flop 301-A, 302-
A is a flip-flop that stores the upper bit and lower bit when the priority is expressed in 2 bits.
Configure A. The priority value is determined by the CPU 300 through signals 310-A and 311-A.
is written using For example, when the priority specifying unit 105-A holds priority 2, flip-flop 301-A is 1 and flip-flop 302-A is 0.

Signals 102-1 and 102-2 are scanning signals 102
These are the upper bit and lower bit when 2 bits are used.

Exclusive OR gates 305-A, 306-A and NOR
Gate 307-A constitutes detection section 104-A. The detection unit 104-A compares the upper bit of the designated priority order with the signal 102-1 and the lower bit of the designated priority order with the signal 102-2, and outputs a match signal 109-A when the two match.

The R.S flip-flop 321-A is a flip-flop that maintains whether output of the selection match signal 116-A is permitted when the peer signal 118 is output. “1” for permission, “0” for prohibition
However, depending on the program, signal 3 is sent from CPU 300.
22-A. R.S flip-flop 321-A, AND gate 325-A,
327-A, OR gate 326-A, and inverter 324-A constitute selection section 115-A. With the connections shown in FIG.
is not outputting, the match signal 109- is always output.
Output a selection match signal 116-A in synchronization with A,
When the same level signal 118 is output, when the flip-flop 321-A is in the enabled state (=1), the selected coincidence signal 11 is output in synchronization with the coincidence signal 109-A.
6-A, and in the prohibited state (=0), does not output the selection match signal 116-A. FIG. 10 is a diagram showing truth values of the selection section 115-A. In addition, in the same figure, it is shown that X may be either 1 or 0.

R.S flip-flop 303-A corresponds to interrupt request control section 106-A. When masking an interrupt request, the CPU 300 uses the signal 312-
A is used to set flip-flop 303-A, and reset when not masking.

The R/S flip-flop 304-A is an interrupt request flag, which corresponds to the interrupt request storage section 107-A, and receives the interrupt request signal 313 from the interrupt source A.
- Set if A is sent, AND gate 30
It is reset when the output of 8-A is "1".

The interrupt reception unit 108-A is composed of an AND gate, and the selection match signal 116-A has a logical value of “1”,
And the flip-flop 303-A of the interrupt request control section 106-A is reset, and the flip-flop 304-A of the interrupt request storage section 107-A is reset.
is set, the interrupt acceptance signal 11
Outputs 0-A.

When the interrupt confirmation signal 314 is sent from the CPU 300, the vector generation unit 309-A transmits the interrupt vector address 313-A to the CPU 300.
Output to 0. R/S as interrupt request flag
- The flip-flop 304-A is configured so that the interrupt acceptance signal 110-A is "1" and the interrupt confirmation signal 31 is "1".
4 is "1", it is reset by the output of AND gate 308-A.

FIG. 8 shows an example of a specific circuit of the control section A101, control section B101', and reception number holding section 117 shown in FIG.

The reception number holding unit 117 includes up-down counters 407, 409, 411, 413 and AND gates 406, 408, 410, 412, 436, 41.
Consists of 9,420,421. The up/down counters 407, 409, 411, 413 are
It stores the number of interrupt receptions for priority levels 0, 1, 2, and 3, respectively. Up-down counters 407, 409, 411, 413 add 1 to their respective held values when count-up signals 441, 443, 445, 447 are input, and when count-down signals 442, 444, 446, 448 are input, Subtract 1 from each retained value. Up-down counter 407, 409, 41
1,413 respectively output zero signals 452, 454, 456, 458 if their held values are 0, and output non-zero signals 451, 45 if they are not 0.
Outputs 3,455,457. Non-zero signal 45
1,453,455,457 correspond to the highest reception priority signal 119.

Figure 9 shows up-down counters 407 and 40.
9 is a circuit diagram showing an example of 9,411,413, and shows the case of 4 bits. It consists of a normal up-down counter 502, an OR gate 501 connected to its clock terminal, an AND gate 503 and an inverter 504 connected to its output.

When the input terminal U is "1" and the input terminal D is "0", the up-down counter 502 operates as an up-counter, adds 1 to its held value, and outputs the result. When the input terminal U is "0" and the input terminal D is "1", the up-down counter 502 operates as a down counter, decrements the held value by 1, and outputs the result. When the held value of the up-down counter 502 is 0, the output of the AND gate 503 becomes "1" and is output as the zero signal from the output 0, and when the held value is not zero,
The output of the AND gate 503 becomes “0” and the output is 0.
The non-zero signal is output from.

By the way, the interrupt acceptance signals 110-A, B,
When either C or D is output, OR gate 40
The interrupt signal 103 which is the output of 5 becomes "1". At this time, AND gates 406, 408, 410, 4
Count up signals 441, 443, 4 from 12
Either one of 45 and 447 outputs. 11th
The figure shows the truth value. When an interrupt is accepted and the interrupt signal 103 becomes "1", the up/down counter 40 corresponding to the priority level is
One of 7,409,411,413 is counted up by 1.

When the interrupt end signal 113 becomes “1”, the up-down counter 407 must be “0”.
Since the output of AND gate 436 becomes "1",
The up-down counter 407 is counted down by one. When the up-down counter 407 is "0", unless the up-down counter 409 is "0", the output of the AND gate 419 is "1", so the up-down counter 409 is
is counted down by 1. When the up-down counters 407 and 409 are both "0", if the up-down counter 411 is not "0",
Since the output of AND gate 420 becomes “1”,
The up-down counter 411 is counted down by one. Up-down counter 407, 40
When both 9 and 411 are "0", unless the up-down counter 413 is "0", the output of the AND gate 421 becomes "1", so the up-down counter 413 counts down by 1.
When the interrupt end signal 113 becomes "1" in this way, the highest priority non-zero up-down counter that holds the number of accepted interrupts for each priority is counted down.

Next, a circuit example of the control section A101 and the control section B101' will be explained.

The control unit A101 controls the T-flip-flop 40.
1,402, AND gates 423, 424, OR gates 405, 422, and NOR gate 404.
4,415, 416, 417, 430, and an OR gate 418.

Signals 102-1 and 102-2, which are the upper and lower bits of the scanning signal 102, are T-
These are the outputs of flip-flops 401 and 402.
Signal 102-2 is inverted at the rising edge of clock signal 403, and signal 102-1 is inverted at the rising edge of clock signal 403.
It is reversed at the falling edge of -2. That is,
T-flip-flops 401 and 402 are quaternary counters that count clock signal 403. The quaternary counter composed of T-flip-flops 401 and 402 is connected to a NOR gate 404.
It is reset when the output becomes a logical value "0".
Clock signal 403 is controlled by reference clock signal 425 from CPU 300.

AND gate 414, 415, 416, 417
and OR gate 418 outputs a signal 435 that resets T-flip-flops 401 and 403 when the priority of the interrupt being accepted and the scanning signal 102 become equal. However, interrupt signal 103
The AND gate 423 prohibits resetting during the period when is "1". For example, if the value held by the up-down counter 407 is "0" and the value held by the up-down counter 409 is "2", that is,
The highest priority of accepted interrupts is 1
In this case, a non-zero signal 453 is output, so
When the scanning signal 102-1 becomes "0" and the scanning signal 102-2 becomes "1" by the AND gate 415, if the interrupt signal 103 is "0", the T-flip-flops 401 and 402 are reset by the signal 435. be done. and scanning signals 102-1, 10
Both 2-2 become "0".

Peer signal 118 is output in synchronization with signal 435. However, when the interrupt signal 103 is "1" by the AND gate 430, its output is prohibited. Therefore, the peer signal 118 is not output at the timing when a new interrupt is accepted.

In the above description of the embodiment, the number of interrupt sources was limited to four, but it goes without saying that the interrupt control device of the present invention is not limited to this and can be applied generally.

(Effects of the Invention) As described above in detail, according to the present invention, with the simple configuration described above, priority can be set arbitrarily for each interrupt factor, and complicated procedures are not required in processing multiple interrupts. Furthermore, it is possible to obtain an interrupt control device that can uniformly control multiple processing of different interrupt requests as well as multiple processing of the same interrupt request.

As the performance of microcomputers and the like has improved and the range of applications has expanded, the types and number of interrupt factors, which have different degrees of importance depending on the application field, has increased. The significance and practical effects of the present invention, which provides an interrupt control device with a simple configuration that uniformly controls a large number of various interrupt factors at the same time, are extremely significant.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the system configuration of an example of a conventional interrupt control device, Fig. 2 is a block diagram of an embodiment of the present invention, and Fig. 3 is a timing diagram showing an example of the output of the scanning signal and the same level signal. Chaat, 4th
The figure shows the function of the selection section, Figures 5 and 6 are timing charts showing examples of its operation, and Figure 7 shows the function of the selection section.
Figures 8 and 9 are partial detailed circuit diagrams, and Figure 1.
0 is a diagram showing truth values showing the function of the selection section of FIG. 8, and FIG. 11 is a diagram showing truth values showing the function of the circuit of FIG. 9. 11 to 14...Interrupt request, 20...Central processing unit, 21...Interrupt control device, 22...Slave interrupt controller, 100-A to 100-D...
Interrupt request, 101...Control unit A, 101'...
Control unit B, 102, 102-1, 120-2...
Scanning signal, 103...Interrupt signal, 104-A~
104-D...detection section, 105-A to 105-D
...Priority order designation section, 106-A to 106-D...
...Interrupt request control unit, 107-A to 107-D...
...Interrupt request storage section, 108-A to 108-D...
...Interrupt acceptance unit, 109-A to 109-D... Match signal, 110-A to 110-D... Interrupt acceptance signal, 113... Interrupt end signal, 115-A...
115-D...Selection section, 116-A to 116-D
...Selection matching signal, 117...Reception number holding unit, 1
18...Same level signal, 119...Highest level signal, 30
0...Central processing unit, 301-A to 304-A,
321-A...R.S flip-flop, 305
-A, 306-A...exclusive OR gate, 307-
A...NOR gate, 308-A, 325-A,
327-A...AND gate, 309-A...Vector generation section, 313...Vector address, 314...
Interrupt confirmation signal, 326-A...OR gate, 3
24-A...Inverter, 310-A, 311-
A, 312-A, 322-A...signal, 401,
402...T-flip-flop, 403...clock signal, 404...NOR gate, 405,
418,422...OR gate, 406,40
8,410,412,414,415,416,
417, 419, 420, 421, 423, 42
4,430,436...AND gate, 407,
409,411,413...Up-down counter, 425,435,441~448,451~
458...Signal, 501...OR gate, 502
...Up-down counter, 503...AND gate, 504...Inverter, A to D, a to d,
d-1 to d-4... Interrupt generation sources.

Claims (1)

[Claims] 1. Interrupt request storage means for storing interrupt requests for each interrupt source, priority order designation means for specifying processing priority for each interrupt request, and scanning signal generation means for outputting a scanning signal that scans the priority order from the highest order. a comparing means for comparing the scanning signal with the contents of the priority order specifying means; an acceptance number holding means for storing the number of accepted interrupts for each priority level; and outputting an index signal indicating the priority order of the interrupts currently being accepted. and the scanning signal outputting means repeatedly outputs the scanning signal at a predetermined period, and when the comparing means detects a match between the scanning signal and the contents of the priority means, the index signal and the An interrupt control device comprising detection control means for controlling priorities based on the contents of an interrupt request storage means and controlling information held in the acceptance number holding means.