JPH03790B2 - - Google Patents
Info
- Publication number
- JPH03790B2 JPH03790B2 JP19212081A JP19212081A JPH03790B2 JP H03790 B2 JPH03790 B2 JP H03790B2 JP 19212081 A JP19212081 A JP 19212081A JP 19212081 A JP19212081 A JP 19212081A JP H03790 B2 JPH03790 B2 JP H03790B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- insulating film
- forming
- film
- silicon thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010408 film Substances 0.000 claims description 36
- 239000010409 thin film Substances 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 17
- 239000003990 capacitor Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 239000010410 layer Substances 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 239000011159 matrix material Substances 0.000 claims description 13
- 239000004973 liquid crystal related substance Substances 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 238000001259 photo etching Methods 0.000 description 11
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/10—Materials and properties semiconductor
- G02F2202/104—Materials and properties semiconductor poly-Si
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Liquid Crystal (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】
本発明は、薄膜素子により形成された、液晶表
示体駆動用アクテイブマトリクス基板に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an active matrix substrate for driving a liquid crystal display formed of thin film elements.
最近、画像表示を目的とした液晶表示体駆動用
アクテイブマトリクス基板の開発が各所で行なわ
れている。特に、透明基板(石英ガラス等)上に
薄膜トランジスタ(以下、TFTと略記)を形成
してこれをスイツチングトランジスタとして用い
る方式のものが注目されている。アクテイブマト
リクス方式による画像表示の一画素に相当する基
本構成単位を第1図に示す。同図において、10
1,102はそれぞれ、i行目、i+1行目のX
側配線(ゲート配線)を、103はi列目のY側
配線(データ配線)を示す。また、104はi行
j列のスイツチング用TFTを、105はアクテ
イブマトリクス基板内に作り込まれた電荷保持用
キヤパシタを、106は液晶表示体に相当するキ
ヤパシタを示す。同図に示すアクテイブマトリク
ス基板は、従来、第2図a〜eに示すごとき工程
で製造されており、最終的に同図eのような構造
となつていた。まず、透明基板(石英ガラス等)
201上にCVD法でSiO2膜202を堆積しホト
エツチによりパターニングを行つて多結晶シリコ
ンの島203を形成する。(第2図a)前記多結
晶シリコンの表面を酸化してゲート酸化膜を形成
し、更に、第二の多結晶シリコン層205を
CVD法で形成する。(第2図b)前記第二の多結
晶シリコン層をホトエツチによりパターニングし
た後、イオン打込みまたは熱拡散によつて不純物
ドープを行う。205及び206の部分に不純物
がドープされる。(第2図c)
層絶縁膜(SiO2膜等)207をCVD法により
堆積させた後、ホトエツチによりコンタクトホー
ル208を形成する。更に、配線金属層209
(アルミ等)をスパツタまたは蒸着により形成し、
ホトエツチによるパターニングを行う。(第2図
d)液晶駆動電極層(ITO膜等)210を形成
し、ホトエツチによるパターニングを行なう。以
上でアクテイブマトリクス基板が完成する。(第
2図e)第2図eにおいて211の部分にスイツ
チング用TFT(第1図の104)を形成してお
り、212の部分に電荷保持用キヤパシタ(第1
図の105)を形成している。 Recently, active matrix substrates for driving liquid crystal displays for the purpose of image display have been developed in various places. In particular, a method in which a thin film transistor (hereinafter abbreviated as TFT) is formed on a transparent substrate (such as quartz glass) and is used as a switching transistor is attracting attention. FIG. 1 shows a basic structural unit corresponding to one pixel of image display using the active matrix method. In the same figure, 10
1 and 102 are X on the i-th line and i+1 line, respectively
103 indicates the side wiring (gate wiring), and 103 indicates the Y-side wiring (data wiring) in the i-th column. Further, 104 indicates a switching TFT in the i-th row and j-th column, 105 indicates a charge retention capacitor built into the active matrix substrate, and 106 indicates a capacitor corresponding to a liquid crystal display. The active matrix substrate shown in FIG. 2 has conventionally been manufactured by the steps shown in FIG. 2 a to e, and the final structure is as shown in FIG. 2 e. First, a transparent substrate (quartz glass, etc.)
A SiO 2 film 202 is deposited on 201 by CVD and patterned by photo-etching to form islands 203 of polycrystalline silicon. (FIG. 2a) The surface of the polycrystalline silicon is oxidized to form a gate oxide film, and then a second polycrystalline silicon layer 205 is formed.
Formed by CVD method. (FIG. 2b) After patterning the second polycrystalline silicon layer by photo-etching, it is doped with impurities by ion implantation or thermal diffusion. Portions 205 and 206 are doped with impurities. (FIG. 2c) After depositing a layer insulating film (such as a SiO 2 film) 207 by CVD, a contact hole 208 is formed by photo-etching. Furthermore, the wiring metal layer 209
(aluminum, etc.) by sputtering or vapor deposition,
Perform patterning by photo etching. (FIG. 2d) A liquid crystal drive electrode layer (ITO film or the like) 210 is formed and patterned by photo-etching. With the above steps, the active matrix board is completed. (Fig. 2 e) In Fig. 2 e, a switching TFT (104 in Fig. 1) is formed in the part 211, and a charge holding capacitor (104 in Fig. 1) is formed in the part 212.
105) in the figure is formed.
このように従来構造により形成された電荷保持
用キヤパシタは、主に次の二つの理由
(i) ゲート配線(第1図101,102)とデー
タ配線(第1図103)との間のリークを防ぐ
と共に耐圧を確認するため層間絶縁膜(第2図
207)の膜厚は10000Å程度と厚くしなくて
はならない。 The charge retention capacitor formed in this conventional structure is mainly used for the following two reasons (i) to prevent leakage between the gate wiring (101, 102 in Figure 1) and the data wiring (103 in Figure 1); In order to prevent this and to confirm the withstand voltage, the interlayer insulating film (207 in FIG. 2) must be as thick as about 10,000 Å.
(ii) 液晶デイスプレイを透過形とするために、光
を通しにくい多結晶シリコン(第2図205)
が占める面積はできるだけ小さくしなくてはな
らない。従つて、キヤパシタ面積は小さくな
る。(ii) Polycrystalline silicon, which is difficult for light to pass through, in order to make the liquid crystal display transmissive (Figure 2 205)
The area it occupies must be kept as small as possible. Therefore, the capacitor area becomes smaller.
によりその容量値をある程度以上大きくすること
はできない。(一画素25000μm2の場合、最大
0.2PF程度)現在、比較的簡単で安価な工程によ
り得られるTFTのオフ電流と液晶のリーク電流
との総和の下限値が100pA〜500pAであることを
考えると十分な表示性能を有する画像デイスプレ
イを得るためには、前記電荷保持用キヤパシタ
(第1図105)の容量値を現状の10倍程度(一
画素25000μm2の場合2pF程度)とする必要があ
る。Therefore, the capacitance value cannot be increased beyond a certain level. (If one pixel is 25000μm2 , the maximum
(approximately 0.2PF) Currently, considering that the lower limit of the total sum of TFT off-current and liquid crystal leakage current obtained through a relatively simple and inexpensive process is 100 pA to 500 pA, it is difficult to create an image display with sufficient display performance. In order to obtain this, it is necessary to increase the capacitance value of the charge holding capacitor (105 in FIG. 1) about 10 times the current value (about 2 pF in the case of one pixel of 25000 μm 2 ).
本発明の目的は、TFT及び薄膜キヤパシタの
製造工程を工夫することにより上述の要求を満た
し、良好な表示性能を有する液晶表示体用アクテ
イブマトリクス基板の構造を提案することにあ
る。 An object of the present invention is to propose a structure of an active matrix substrate for a liquid crystal display that satisfies the above requirements and has good display performance by improving the manufacturing process of TFTs and thin film capacitors.
以下に、図面(第3図a〜f)を用いて本発明
の骨子を説明する。本発明の構造を有するアクテ
イブマトリクス基板は次のごとく製造される。ま
ず、従来同様に透明基板(石英基板等)301上
にCVD法でSiO2膜302を堆積(デポジシヨン)
した後、その上に第一の多結晶シリコン層30
3,304を堆積する。更に、前記第一の多結晶
シリコン層の上全面にCVD法によりSiO2等の膜
を堆積させた後、ホトエツチによつて前記SiO2
等の膜をパターニングし305を得る。次に、3
05をマスクとし、イオン打込みまたは熱拡散に
よつて不純物をドープする。これにより、不純物
ドープされない多結晶シリコン部分303及び不
純物ドープされた部分304が得られる。303
は、後にTFTのチヤネルが形成される部分であ
る。(第3図a)前記第一の多結晶シリコン層を
ホトエツチによりパターニングする。 The gist of the present invention will be explained below using the drawings (Fig. 3 a to f). An active matrix substrate having the structure of the present invention is manufactured as follows. First, a SiO 2 film 302 is deposited (deposition) on a transparent substrate (quartz substrate, etc.) 301 using the CVD method as in the conventional method.
After that, a first polycrystalline silicon layer 30 is applied thereon.
Deposit 3,304. Furthermore, after depositing a film such as SiO 2 on the entire surface of the first polycrystalline silicon layer by CVD, the SiO 2 film is deposited by photo-etching.
A film 305 is obtained by patterning the film. Next, 3
05 as a mask, impurities are doped by ion implantation or thermal diffusion. This results in a polycrystalline silicon portion 303 that is not doped with impurities and a portion 304 that is doped with impurities. 303
is the part where the TFT channel will be formed later. (FIG. 3a) The first polycrystalline silicon layer is patterned by photo-etching.
306,307はTFTのソース・ドレインと
なる部分であり、308は薄膜キヤパシタの電極
となる部分である。(第3図b)
次に、第一の多結晶シリコン層303,30
6,307,308の表面を酸化し、TFTのゲ
ート酸化膜309及びキヤパシタの絶縁膜310
を得る。全面に第二の多結晶シリコン層311を
堆積させる。(第3図c)
ホトエツチにより前記第二の多結晶シリコン層
311のパターニングを行ない、ゲート電極31
2及びキヤパシタ電極313を得る。しかる後、
イオン打込みまたは熱拡散により全面に不純物を
ドープする。この際、306,307及び308
の一部には第3図aのものと合わせて二重に不純
物ドープが行なわれることになる。また、305
のパターン領域が312のパターン領域を完全に
包含するようにマスク設計することによりゲート
電極オーバーラツプによるTFTの寄生容量を小
さくすることができる。(第3図d)
層間絶縁膜(SiO2膜等)をCVD法により全面
に堆積させた後、ホトエツチによりコンタクトホ
ール318,319,320を形成する。更に、
金属配線層(アルミ等)をスパツタまたは蒸着に
より全面に形成した後、ホトエツチによるパター
ニングを行なつてパターン321,322,32
3を得る。(第3図e)
最後に、液晶駆動電極層(ITO膜等)を全面に
形成した後ホトエツチによるパターニングを行な
つて液晶駆動電極324を得る。 306 and 307 are portions that will become the source and drain of the TFT, and 308 is a portion that will be the electrode of the thin film capacitor. (FIG. 3b) Next, first polycrystalline silicon layers 303, 30
6, 307, and 308 to form a TFT gate oxide film 309 and a capacitor insulating film 310.
get. A second polycrystalline silicon layer 311 is deposited over the entire surface. (FIG. 3c) The second polycrystalline silicon layer 311 is patterned by photoetching, and the gate electrode 31 is patterned.
2 and a capacitor electrode 313 are obtained. After that,
The entire surface is doped with impurities by ion implantation or thermal diffusion. At this time, 306, 307 and 308
A portion of the wafer is doped with impurities in combination with that of FIG. 3a. Also, 305
By designing the mask so that the pattern region 312 completely covers the pattern region 312, the parasitic capacitance of the TFT due to gate electrode overlap can be reduced. (FIG. 3d) After depositing an interlayer insulating film (such as a SiO 2 film) over the entire surface by CVD, contact holes 318, 319, and 320 are formed by photoetching. Furthermore,
After forming a metal wiring layer (aluminum, etc.) on the entire surface by sputtering or vapor deposition, patterning is performed by photoetching to form patterns 321, 322, 32.
Get 3. (FIG. 3e) Finally, a liquid crystal drive electrode layer (such as an ITO film) is formed on the entire surface and patterned by photo-etching to obtain a liquid crystal drive electrode 324.
以上で本発明の構造を有するアクテイブマトリ
クス基板が完成する。(第3図f)第3図fにお
いて薄膜キヤパシタは二つの多結晶シリコン電極
308と313との間及び多結晶シリコン電極3
13と駆動電極324との間に形成されている。
通常、酸化膜310の厚さは層間絶縁膜316の
膜厚に比べ十分の一程度に形成される。従つて、
本発明を適用することにより、従来に比較して十
倍以上の容量値を有する電荷保持用キヤパシタを
作り込むことが可能となる。しかも、製造に要す
る工程数及びコストは20%程度の上昇に押さえら
れる。 With the above steps, an active matrix substrate having the structure of the present invention is completed. (FIG. 3 f) In FIG. 3 f, the thin film capacitor is located between the two polycrystalline silicon electrodes 308 and 313 and
13 and the drive electrode 324.
Typically, the thickness of the oxide film 310 is approximately one-tenth of the thickness of the interlayer insulating film 316. Therefore,
By applying the present invention, it becomes possible to fabricate a charge retention capacitor having a capacitance value ten times or more compared to the conventional one. Moreover, the number of steps and costs required for manufacturing can be suppressed to an increase of about 20%.
上述の如く本発明は、透明基板上に第一シリコ
ン薄膜を堆積し、該第一シリコン薄膜上に第一絶
縁膜を形成し、該第一絶縁膜をパターニング後、
該第一絶縁膜をマスクとし、該第一シリコン薄膜
に不純物を導入する工程、該第一シリコン薄膜を
パターニングし複数の島状領域を形成後、該第一
絶縁膜を除去する工程、該島状領域上に絶縁膜を
形成する工程、該絶縁薄膜上に第二シリコン薄膜
を形成し、該第二シリコン薄膜をパターニングし
ゲート電極、キヤパシタ電極を得る工程、該第二
シリコン薄膜上に層間絶縁膜を形成後、コンタク
トホールを形成し、導電配線層を形成する工程、
該層間絶縁膜上に液晶駆動用透明電極を形成する
工程よりなるようにしたから、薄膜トランジスタ
のゲート絶縁膜とキヤパシタの絶縁膜とを同時形
成することができ、かつ容量のすぐれたNOS薄
膜キヤパシタを形成することができる。 As described above, in the present invention, a first silicon thin film is deposited on a transparent substrate, a first insulating film is formed on the first silicon thin film, and after patterning the first insulating film,
A step of introducing an impurity into the first silicon thin film using the first insulating film as a mask, a step of patterning the first silicon thin film to form a plurality of island-like regions, and then removing the first insulating film, and a step of removing the first insulating film. forming an insulating film on the insulating thin film, forming a second silicon thin film on the insulating thin film and patterning the second silicon thin film to obtain a gate electrode and a capacitor electrode, interlayer insulation on the second silicon thin film After forming the film, forming a contact hole and forming a conductive wiring layer;
Since the process consists of forming a transparent electrode for driving the liquid crystal on the interlayer insulating film, the gate insulating film of the thin film transistor and the insulating film of the capacitor can be formed simultaneously, and the NOS thin film capacitor with excellent capacitance can be manufactured. can be formed.
第1図は、アクテイブマトリクス基板を用いた
液晶デイスプレイの一画素の構成を説明するため
の図。第2図a〜eは、従来のアクテイブマトリ
クス基板製造工程を説明するための図。第3図a
〜fは、本発明のアクテイブマトリクス基板製造
工程を説明するための図。
FIG. 1 is a diagram for explaining the configuration of one pixel of a liquid crystal display using an active matrix substrate. FIGS. 2a to 2e are diagrams for explaining the conventional active matrix substrate manufacturing process. Figure 3a
-f are diagrams for explaining the active matrix substrate manufacturing process of the present invention.
Claims (1)
第一シリコン薄膜上に第一絶縁膜を形成し、該第
一絶縁膜をパターニング後、該第一絶縁膜をマス
クとし、該第一シリコン薄膜に不純物を導入する
工程、該第一シリコン薄膜をパターニングし複数
の島状領域を形成後、該第一絶縁膜を除去する工
程、該島状領域上に絶縁膜を形成する工程、該絶
縁薄膜上に第二シリコン薄膜を形成し、該第二シ
リコン薄膜をパターニングしゲート電極、キヤパ
シタ電極を得る工程、該第二シリコン薄膜上に層
間絶縁膜を形成後、コンタクトホールを形成し、
導電配線層を形成する工程、該層間絶縁膜上に液
晶駆動用透明電極を形成する工程よりなることを
特徴とするアクテイブマトリクス基板の製造方
法。1 Depositing a first silicon thin film on a transparent substrate, forming a first insulating film on the first silicon thin film, patterning the first insulating film, using the first insulating film as a mask, and depositing the first silicon thin film on the first silicon thin film. a step of introducing impurities into a thin film, a step of patterning the first silicon thin film to form a plurality of island-like regions, a step of removing the first insulating film, a step of forming an insulating film on the island-like regions, and a step of forming the insulating film on the island-like regions. forming a second silicon thin film on the thin film, patterning the second silicon thin film to obtain a gate electrode and a capacitor electrode, forming an interlayer insulating film on the second silicon thin film, and then forming a contact hole;
A method for manufacturing an active matrix substrate, comprising the steps of forming a conductive wiring layer and forming a transparent electrode for driving a liquid crystal on the interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19212081A JPS5893269A (en) | 1981-11-30 | 1981-11-30 | Active matrix substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19212081A JPS5893269A (en) | 1981-11-30 | 1981-11-30 | Active matrix substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5893269A JPS5893269A (en) | 1983-06-02 |
| JPH03790B2 true JPH03790B2 (en) | 1991-01-08 |
Family
ID=16285998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19212081A Granted JPS5893269A (en) | 1981-11-30 | 1981-11-30 | Active matrix substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5893269A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015033738A1 (en) | 2013-09-03 | 2015-03-12 | 東亞合成株式会社 | Adhesive composition |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61102628A (en) * | 1984-10-25 | 1986-05-21 | Sony Corp | Liquid crystal display device |
| JP2589327B2 (en) * | 1987-11-14 | 1997-03-12 | 株式会社リコー | Method for manufacturing thin film transistor |
| JP2590973B2 (en) * | 1987-11-25 | 1997-03-19 | 日本電装株式会社 | Method for manufacturing semiconductor device |
-
1981
- 1981-11-30 JP JP19212081A patent/JPS5893269A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015033738A1 (en) | 2013-09-03 | 2015-03-12 | 東亞合成株式会社 | Adhesive composition |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5893269A (en) | 1983-06-02 |
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