JPH0379433U - - Google Patents

Info

Publication number
JPH0379433U
JPH0379433U JP1989140899U JP14089989U JPH0379433U JP H0379433 U JPH0379433 U JP H0379433U JP 1989140899 U JP1989140899 U JP 1989140899U JP 14089989 U JP14089989 U JP 14089989U JP H0379433 U JPH0379433 U JP H0379433U
Authority
JP
Japan
Prior art keywords
circuit board
conductive foil
semiconductor device
semiconductor
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1989140899U
Other languages
English (en)
Other versions
JPH0617288Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989140899U priority Critical patent/JPH0617288Y2/ja
Publication of JPH0379433U publication Critical patent/JPH0379433U/ja
Application granted granted Critical
Publication of JPH0617288Y2 publication Critical patent/JPH0617288Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は、本考案の位置実施例の断面図であり
、第２図は第１図の平面図であり、第３図は、従
来例として示した半導体装置の断面図である。 １……回路基板、２……導電箔、３……半導体
ペレツト、４……露出部、５……接着剤、７……
ボンデイングパターン、８……ワイヤ、９……樹
脂、１０……パツト。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 導電箔付回路基板に直接半導体ペレツトを
    接着し、ワイヤボンデイングにより前記半導体ペ
    レツトと前記回路基板上のボンデイングパターン
    とを電気的に接続した後、前記半導体ペレツト全
    体を樹脂により密封した半導体装置において、 前記半導体ペレツト底面の領域に対応する前記
    回路基板上の領域に一部前記導電箔を形成しない
    回路基板露出部を設けて前記導電箔を形成したこ
    とを特徴とする半導体装置。 (2) 前記露出部が円形であることを特徴とする
    請求項１記載の半導体装置。
JP1989140899U 1989-12-04 1989-12-04 半導体装置 Expired - Lifetime JPH0617288Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989140899U JPH0617288Y2 (ja) 1989-12-04 1989-12-04 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989140899U JPH0617288Y2 (ja) 1989-12-04 1989-12-04 半導体装置

Publications (2)

Publication Number Publication Date
JPH0379433U true JPH0379433U (ja) 1991-08-13
JPH0617288Y2 JPH0617288Y2 (ja) 1994-05-02

Family

ID=31687837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989140899U Expired - Lifetime JPH0617288Y2 (ja) 1989-12-04 1989-12-04 半導体装置

Country Status (1)

Country Link
JP (1) JPH0617288Y2 (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55173175U (ja) * 1979-05-29 1980-12-12
JPS5810381U (ja) * 1981-07-15 1983-01-22 松下電器産業株式会社 リ−ド線保持具の取付装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55173175U (ja) * 1979-05-29 1980-12-12
JPS5810381U (ja) * 1981-07-15 1983-01-22 松下電器産業株式会社 リ−ド線保持具の取付装置

Also Published As

Publication number Publication date
JPH0617288Y2 (ja) 1994-05-02

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