JPH0390460U - - Google Patents
Info
- Publication number
- JPH0390460U JPH0390460U JP15235789U JP15235789U JPH0390460U JP H0390460 U JPH0390460 U JP H0390460U JP 15235789 U JP15235789 U JP 15235789U JP 15235789 U JP15235789 U JP 15235789U JP H0390460 U JPH0390460 U JP H0390460U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- region
- field effect
- effect transistor
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 2
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
第１図は本考案の一実施例による縦型電界効果
トランジスタの縦断面図、第２図は従来の縦型電
界効果トランジスタの縦断面図である。
１……Ｎ型半導体基板、２……Ｐ型ベース拡散
層、３……Ｎ型ソース拡散層、４……ゲート絶縁
膜（ゲート酸化膜）。
FIG. 1 is a vertical cross-sectional view of a vertical field effect transistor according to an embodiment of the present invention, and FIG. 2 is a vertical cross-sectional view of a conventional vertical field effect transistor. 1... N-type semiconductor substrate, 2... P-type base diffusion layer, 3... N-type source diffusion layer, 4... gate insulating film (gate oxide film).
Claims (1)
に互いに対向するようにベース領域とその内部の
ソース領域とを有し、対向する前記ソース領域間
には前記ベース領域上で薄くかつ前記半導体基板
上で厚く形成されているゲート絶縁膜を有するこ
とを特徴とする縦型電界効果トランジスタ。 (2) 前記ゲート絶縁膜の厚い部分は選択酸化に
よつて形成されていることを特徴とする実用新案
登録請求の範囲第(1)項記載の縦型電界効果トラ
ンジスタ。[Claims for Utility Model Registration] (1) A semiconductor substrate having a base region and a source region therein facing each other on the surface of a semiconductor substrate acting as a drain, and a region on the base region between the opposing source regions. A vertical field effect transistor characterized by having a gate insulating film formed thinly and thickly on the semiconductor substrate. (2) The vertical field effect transistor according to claim 1, wherein the thick portion of the gate insulating film is formed by selective oxidation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15235789U JPH0390460U (en) | 1989-12-27 | 1989-12-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15235789U JPH0390460U (en) | 1989-12-27 | 1989-12-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0390460U true JPH0390460U (en) | 1991-09-13 |
Family
ID=31698625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15235789U Pending JPH0390460U (en) | 1989-12-27 | 1989-12-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0390460U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008262982A (en) * | 2007-04-10 | 2008-10-30 | Toyota Central R&D Labs Inc | Group III nitride semiconductor device and manufacturing method thereof |
-
1989
- 1989-12-27 JP JP15235789U patent/JPH0390460U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008262982A (en) * | 2007-04-10 | 2008-10-30 | Toyota Central R&D Labs Inc | Group III nitride semiconductor device and manufacturing method thereof |
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